Fishing – trapping – and vermin destroying
Patent
1991-03-25
1993-04-13
Thomas, Tom
Fishing, trapping, and vermin destroying
437 40, 437 41, 437 44, 437228, 437944, H01L 2170
Patent
active
052022722
ABSTRACT:
A method of forming a semiconductor structure comprising the steps of: providing a body of semiconductor material including at least one generally planar surface; forming a mesa having at least one generally vertical wall over the planar surface; forming a layer of material generally conformally over the mesa and the planar surface so as to form a vertical spacer on the vertical wall; forming a protective mask selectively on the upper portion of the vertical spacer; and using the protective mask to etch and remove the unmasked portions of the layer of material and the mesa while leaving the vertical spacer.
The process is used to form an FET by forming a gate insulating layer underneath of the vertical spacer, the vertical spacer being selected to comprise a conductive gate material such as doped polysilicon. The vertical gate structure is then used as a mask to dope the source and drain regions.
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Hsieh Chang-Ming
Hsu Louis L.
Kumar Shantha A.
Tien Zu-Jean
Brandt Jeffrey L.
Huberfeld Harold
International Business Machines - Corporation
Thomas Tom
LandOfFree
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