Field effect transistor (FET) device having corrugated...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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C257S317000, C257SE29028

Reexamination Certificate

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10632379

ABSTRACT:
Within both a field effect transistor (FET) device and a method for fabricating the field effect transistor (FET) device there is provided: (1) a semiconductor substrate; (2) a gate electrode formed over the semiconductor substrate and covering a channel region within the semiconductor substrate; and (3) a pair of source/drain regions formed within the semiconductor substrate and separated by the channel region within the semiconductor substrate. Within both the field effect transistor (FET) device and the method for fabricating the field effect transistor (FET) device, at least one of: (1) an interface of the channel region covered by the gate electrode; and (2) an upper surface of the gate electrode, is corrugated.

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patent: 5365078 (1994-11-01), Hayashi et al.
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patent: 6677202 (2004-01-01), Semple et al.
Sallagoity et al, “Analysis of Width Edge Effects in Advanced Isolation Schemes for Deep Submicron CMOS Technologies”, IEEE Trans. on Electron Devices, 44(11), Nov. 1996, pp. 1900-1905.
Matsuda et al, Novel Corner Rounding Process of Shallow Trench Isolation Utilizing MSTS (Micro-Structure Transformation of silicon). IEEE IEDM98, pp. 137-140.

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