Field-effect transistor devices

Details Field-effect transistor devices Field-effect transistor devices

1987-03-20

1989-06-20

Edlow, Martin H.

357 233, 357 2312, 357 67, H01L 2978

Patent

active

048413461

ABSTRACT:
A MOSFET utilizes a buried channel structure comprising a buried channel between a source electrode and a drain electrode. The device also comprises a gate electrode made of material whose Fermi level is located between a conduction band and a valency band of a semiconductor. An impurity concentration in the substrate is relatively high because of buried channel structure.

REFERENCES:
patent: 4434433 (1984-02-01), Nishizawa
patent: 4612565 (1986-09-01), Shimizu et al.
Oka et al., "Two Dimensional . . . MOSFETS", IEEE IEDM, 1979, pp. 30-33.
Nishizawa, "A Limitation . . . Memories", (pp. 705-714), IEEE Journal of Solid State Circuits, vol. SC-15, No. 4, Aug. 1980.
Technical Digest of IEDM 84, pp. 642-646. E. P. Jacobs et al.; "N- and P-Well Process Compatibility in a 1 .mu.m-CMOS Technology".
Technical Digest of IEDM 85, pp. 238-241, M. Nakahara et al., "Relief of Hot Carrier Constraint on Submicron CMOS Devices by Use of a Buried Channel Structure".

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