Field-effect transistor device having a uniquely arranged...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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C331S096000, C257S275000, C257S277000

Reexamination Certificate

active

06737687

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to field-effect transistor devices incorporated in, for example, amplifier circuits, oscillation circuits, and other electronic apparatuses.
2. Description of the Related Art
FIG. 8A
is a schematic plan view showing an example of a field-effect transistor device (FET device)
FIG. 8B
is a schematic sectional view taken along the line A—A of the FET device of
FIG. 8A
as disclosed in Japanese Unexamined Patent Application Publication No. 63-164504. An FET device
30
of
FIGS. 8A and 8B
has a semiconductor substrate
31
made of GaAs, etc., and impurity ions, such as Si
+
, are implanted into the central portion of the semiconductor substrate
31
, so as to form an active layer
32
. A gate electrode
33
is formed on the surface of the active layer
32
, and also, a source electrode
34
and a drain electrode
35
are formed so as to sandwich the gate electrode
33
with a space defined therebetween. The active layer
32
, the gate electrode
33
, the source electrode
34
, and the drain electrode
35
define an FET portion.
On the surface of the semiconductor substrate
31
, an electrode
36
used for a line to make a connection to the gate, connected to the gate electrode
33
, is formed at the upper left portion of FIG.
8
A. An electrode
37
used for a line to make a connection to the source, connected to the source electrode
34
, is formed at the upper right portion of FIG.
8
A. Furthermore, an electrode
38
used for a line to make a connection to the drain, connected to the drain electrode
35
, is formed at the lower half portion of FIG.
8
A.
The gate-connection-line electrode
36
, the source-connection-line electrode
37
, and the drain-connection-line electrode
38
define a signal line connected to the FET portion. That is, the drain-connection-line electrode
38
is grounded. The drain-connection-line electrode
38
has a portion
38
a
opposing the gate-connection-line electrode
36
with a space defined therebetween, and a portion
38
b
opposing the source-connection-line electrode
37
with a space defined therebetween. An electrode pair
40
of electrode portion
3
Ba and gate-connection-line electrode
36
, and an electrode pair
41
of electrode portion
38
b
and source-connection-line electrode
37
each functions as a slot line. The electrode pair
40
defines a FET input line, and the electrode pair
41
defines a FET output line.
In this FET device
30
, for example, when a signal is input to the gate electrode
33
via the FET input line
40
, the signal amplified by the active layer
32
is output externally through the FET output line
41
.
In the configuration of the FET device
30
, the gate electrode
33
has a configuration that extends along the conduction direction of the signal. For this reason, a phase difference occurs between the signal at the base-end portion of the gate electrode
33
and the signal at the front-end portion of the gate electrode
33
, and when a high-frequency signal flows, the phase difference cannot be ignored. For example, when the phase difference between the signal at the base-end portion of the gate electrode
33
and the signal at the front-end portion thereof is approximately &lgr;/4 to &lgr;/2, the signal which is amplified on the basis of the signal at the base-end portion of the gate electrode
33
, and the signal which is amplified on the basis of the signal at the front-end portion become 180° out of phase with each other. As a result, portions of the signals amplified by the FET portion cancel each other, presenting a problem in that the gain (power amplification efficiency) of the FET portion is decreased.
SUMMARY OF THE INVENTION
In order to overcome the problems described above, preferred embodiments of the present invention provide a field-effect transistor device that is capable of increasing the gain without suffering the disadvantages and problems described above.
According to a preferred embodiment of the present invention, a field-effect transistor device includes a field-effect transistor portion including a gate electrode, a source electrode, and a drain electrode, the gate electrode being located on the surface of an active area located on a semiconductor substrate, and the source electrode and the drain electrode being arranged in such a manner so as to sandwich the gate electrode with a space provided therebetween; a gate-connection-line electrode defining a line for making a connection to the gate electrode; a source-connection-line electrode defining a line for making a connection to the source electrode, the gate-connection-line electrode and the source-connection-line electrode being arranged such that respective portions thereof oppose each other with a space provided therebetween; and an electrode used defining a line for making a connection to the drain electrode arranged in such a manner that a portion thereof opposes the gate-connection-line electrode with a space provided therebetween, the gate-connection-line electrode, the source-connection-line electrode, and the drain-connection-line electrode being disposed on the surface of the semiconductor substrate which is coplanar with respect to the surface on which the gate electrode, the source electrode, and the drain electrode are disposed, wherein one of the electrode pair portion where the gate-connection-line electrode opposes the source-connection-line electrode and the electrode pair portion where the gate-connection-line electrode opposes the drain-connection-line electrode functions as a slot line on the input side for inputting a signal to the field-effect transistor portion and the other of the electrode pair portion where the gate-connection-line electrode opposes the source-connection-line electrode and the electrode pair portion where the gate-connection-line electrode opposes the drain-connection-line electrode functions as a slot line on the output side from which a signal is output from the field-effect transistor portion, and wherein the gate electrode has a configuration which extends along a direction that is substantially perpendicular to the conduction direction of the signal flowing through the slot line on the input side or along a direction inclined with respect to the conduction direction of the signal flowing through the slot line on the input side.
The source-connection-line electrode and the drain-connection-line electrode may be arranged adjacent to each other with a space provided therebetween, and a cut-out portion may be formed in at least one of the electrode portion on the drain-connection-line electrode side in the source-connection-line electrode and the electrode portion on the source-connection-line electrode side in the drain-connection-line electrode. As a result, the space between the source-connection-line electrode and the drain-connection-line electrode is increased.
The slot line on the input side and the slot line on the output side may be arranged along approximately the same straight line and such that the field-effect transistor portion is disposed therebetween.
A plurality of sets of the gate electrode, the source electrode, and the drain electrode may be disposed on the same surface of the semiconductor substrate, the field-effect transistor device may include a plurality of field-effect transistor portions, and a slot line on the input side and a slot line on the output side, corresponding to each of the plurality of field-effect transistor portions, may be disposed on the semiconductor substrate.
An even number of field-effect transistor portions may be arranged with a space provided therebetween on the semiconductor substrate, and the entire electrode pattern of a plurality of sets of the gate electrode, the source electrode, and the drain electrode, the gate-connection-line electrode, the source-connection-line electrode, and the drain-connection-line electrode, which are disposed on the surface of the semiconductor substrate, may be arranged to have a pattern shape which is approximat

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