Field effect transistor circuit arrangement

Details Field effect transistor circuit arrangement Field effect transistor circuit arrangement

1981-08-28

1983-07-19

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307571, 307296R, H03K 1710, H03K 17687

Patent

active

043945902

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. TECHNICAL FIELD
The present invention relates to a field effect transistor circuit arrangement having a plurality of insulated gate field effect transistors such as MOS type field effect transistors (referred to as MOS FET hereinafter) connected in series to be operable under a high voltage condition.
2. BACKGROUND ART
The voltage withstand between the drain and source of a MOSFET currently commercially available is substantially 400 V at most. Accordingly, in order to operate the MOSFET at 300 V or more for practical use, it is necessary to connect a plurality of MOSFETs in series to increase the voltage withstand. To this end, circuit arrangements as shown in FIGS. 1 and 2 have hitherto been used.
In a circuit arrangement shown in FIG. 1, a pulse transformer is employed to provide two or more gate drive signals which are isolated from each other. That is, in FIG. 1, a gate drive signal Vin is applied to a primary winding W1 of a pulse transformer PT. Individual output pulses obtained from secondary windings W2 and W3 are applied respectively to the gates of n-channel MOSFETs Q1 and Q2 connected in series. ZD1 and ZD2 are protective Zener diodes each for restricting the gate input signal so that a voltage between the gate and source does not exceed a breakdown voltage between the gate and source. The drain of the MOSFET Q1 is connected to a power source Vs via a load resistor RL and the source of the MOSFET Q1 is connected to the drain of the MOSFET Q2, the source of which is connected to a common potential point. This drive method which uses the pulse transformer has frequently been used for the series operation of bipolar transistors and thyristers, or the like. In the drive method, however, the operating frequency range of the gate drive signal Vin is limited by characteristics of the pulse transformer used and in particular the limited frequency range causes a problem when the operating frequency is low, ranging in the order to several KHz to 100 KHz so that the conduction period of time is long.
A circuit arrangement of FIG. 2 illustrates a drive method of the type in which a pulsive drive signal is applied to one of two elements for series operation and a DC voltage is applied to the other element. In FIG. 2, like reference numerals are used to designate like portions shown in FIG. 1. In the conventional drive method shown in FIG. 2, the gate drive signal Vin is directly applied to the gate of the MOSFET Q2 and a DC voltage Vdc is applied to the gate of another MOSFET Q1, through a parallel circuit consisting of a resistor R1 and a capacitor C1. A parallel circuit consisting of a resistor R2 and a capacitor C2 is connected between the gate and drain of the MOSFET Q1. Further, the resistors R1 and R2 form a voltage divider for determining an actual bias voltage applied to the gate of the MOSFET Q1. The capacitors C1 and C2 are used for correcting transient voltage share across the MOSFET Q1 at the time of the switching. The respective circuit constants of those resistors and capacitors have been selected to be C1/C2.apprxeq.R2/R1 and the capacitance values of the capacitors C1 and C2 have been extremely small, for example, several tens pF. According to this drive method, the operating frequency range is not limited, unlike the method shown in FIG. 1. If, however, the power source voltage (e.g. 400 V) of the MOSFET is taken into consideration, it is necessary to provide a power source (e.g. 10 V) for the gate drive independently or to apply a given voltage from the power source of MOSFET to the gate of the MOSFET through a voltage dividing circuit having a large power consumption. In this respect, the drive method has problems in terms of cost and convenience.


DISCLOSURE OF INVENTION

Accordingly, an object of the present invention is to provide a field effect transistor circuit arrangement which, in driving field effect transistors connected in series, eleminates the defects of the above-described conventional drive methods without the restriction of the operating frequency and the

REFERENCES:
patent: 3007061 (1961-10-01), Gindi
patent: 4100438 (1978-07-01), Yokoyama
patent: 4317055 (1982-02-01), Yoshida et al.

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