Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2000-09-19
2003-04-15
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S197000
Reexamination Certificate
active
06548838
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to afield-effect transistor, a bipolar transistor, and methods of fabricating the same.
A typical mobile telephone has a transmit/receive switching device for switching a single antenna between transmission and reception. As the transmit/receive switching device, an RF switching device composed of a field-effect transistor (FET) using GaAs has been used, of which a reduction in loss has been demanded strongly.
To achieve a loss reduction in the RF switching device, it is necessary to reduce the source-to-drain resistance of the switching device in the on state and reduce the source-to-drain capacitance of the switching device in the off state.
Compared with the PDC (personal digital cellular) method standardized in Japan, the GSM (global system for mobile communication) method, which is a communication method standardized in European countries, features a large antenna output. To provide a large power handling capability even at a low control voltage, therefore, a multigate FET device in which one FET device has a plurality of gate electrodes should be used. However, since a conventional multigate FET device has a high on-state resistance, the insertion of the FET device causes a large insertion loss.
As an approach to the solution of the problem, the use of a FET device having a multigate electrode formed by self alignment as the RF switching device may be considered. By using the RF switching device having the self-aligned multigate electrode, the distance between the source and drain electrodes is reduced so that the source-to-drain resistance of the device in the on state is reduced. In addition, since the self-aligned gate of the FET device is formed by self alignment relative to the source and drain electrodes thereof, a mask placement error does not occur during the formation of the gate electrode by photolithography.
Of heterojunction bipolar transistors (HBTs) which are active devices different from FETs, the one having the base electrode formed by self alignment relative to the emitter electrode is effective in reducing the base resistance. In the case of the HBT device also, a mask placement error does not occur during the formation of the base electrode by photolithography, similarly to the aforesaid FET device having the gate electrode formed by self alignment.
A conventional FET device having a self-aligned gate electrode will be described with reference to the drawings.
FIG. 11
shows a cross-sectional structure in the direction of the gate length of the conventional FET device disclosed in Japanese Unexamined Patent Publication No. HEI 8-115924.
As shown in
FIG. 11
, a conductive layer (channel layer)
102
composed of n-type GaAs doped with silicon (Si) as an impurity and a Schottky layer
103
composed of undoped aluminum gallium arsenide (AlGaAs) are formed successively on a semi-insulating substrate
101
made of gallium arsenide (GaAs). An isolation region
104
as an insulated region is formed in the formed conductive layer
102
and Schottky layer
103
to reach the semi-insulating substrate
101
and electrically insulated from other devices (not shown).
A pair of contact layers
105
each composed of n
+
-type indium gallium arsenide heavily doped with Si are formed on a region of the Schottky layer
103
on which the device is to be formed. Ohmic electrodes
106
each composed of a refractory metal such as tungsten silicide (WSi) and serving as a source or drain electrode are formed on the pair of contact layers
105
, respectively.
On a region of the Schottky layer
103
lying between the contact layers
105
, a gate electrode
107
A is formed at a distance from the side surfaces of the contact layers
105
. Metal layers
107
B composed of the same material as composing the gate electrode
107
A are formed on the respective ohmic electrodes
106
. The entire surface of the FET device including the gate electrode
107
A and the metal layers
107
B is covered with a protective insulating film
108
composed of a silicon oxide or the like. On the portions of the protective insulating film
108
located above the respective metal layers
107
B, there are disposed Au wiring layers
109
for electrical connection with the respective metal layers
107
B.
A method of fabricating the FET device thus structured will be described herein below.
First, the conductive layer
102
, the Schottky layer
103
, and the contact layer
105
are epitaxially grown in succession on the semi-insulating substrate
101
. Subsequently, a metal film composed of WSi for forming the ohmic electrodes is formed by sputtering over the entire surface of the contact layer
105
.
Next, the metal film is patterned by reactive anisotropic dry etching by using, as a mask, a resist pattern formed by photolithography to have the ohmic electrode pattern, whereby the ohmic electrodes
106
composed of Wsi are formed.
Next, isotropic wet etching is performed with respect to the contact layer
105
by using a solution mixture of, e.g., phosphoric acid, aqueous hydrogen peroxide, and water, thereby removing the portion of the contact layer
105
corresponding to the gate electrode. Then, a specified amount of side etching is performed with respect to the portions of the contact layers
105
located under the ohmic electrodes
106
, thereby forming each of the contact layers
105
into an undercut configuration relative to the ohmic electrodes
106
.
Next, the isolation region
104
is formed in the peripheral portion of the FET device by ion implantation. Thereafter, a metal film for forming the gate electrode is vapor deposited to a thickness smaller than the film thickness of the contact layer
105
over the entire surface of the semi-insulating substrate
101
, thereby forming the gate electrode
107
A by self alignment relative to the ohmic electrodes
106
.
Next, the protective insulating film
108
composed of the silicon oxide is formed over the entire surface of the semi-insulating substrate
101
. After that, the Au wiring layers
109
are formed by plating in the contact portions of the protective insulating film
108
for contact with the ohmic electrodes
106
.
If the FET device having the self-aligned gate electrode is to be used as the switching device, it is required to reduce the source-to-drain resistance of the switching device in the on state and reduce the source-to-drain capacitance of the switching device in the off state, as stated previously.
In reducing the off-state source-to-drain parasitic capacitance of the FET device having the gate electrode
107
A formed by self alignment shown in
FIG. 11
, it is effective to reduce the area of each of the source and drain electrodes (ohmic electrodes
106
) to the order of micrometers. By miniaturizing the source and drain electrodes, the chip size can be reduced drastically.
However, the conventional method of fabricating the field-effect transistor has the problem of an increase in contact resistance due to a reduction in contact area between each of the ohmic electrode
106
and the contact layer
105
, which is caused by side etching (undercut) proceeding at the portions of the contact layers
105
underlying the ohmic electrodes
106
in the wet etching process performed with respect to the contact layers
105
. If the ohmic electrode
106
with a width of 2.0 &mgr;m is etched by wet etching to a depth of 0. 5 &mgr;m, e.g., the width of the portion of the contact layer
105
underlying the ohmic electrode
106
becomes 1 &mgr;m and the contact resistance is approximately doubled. This presents a new problem encountered by the ongoing miniaturization of the FET device having the self-aligned gate electrode.
To reduce the contact resistance, non-alloy electrodes which do not form alloy layers at the interfaces with the contact layers
105
and therefore do not require a heat treatment may be used as the ohmic electrodes
106
. In the case of using a multilayer structure of, e.g., titanium (Ti), platinum (Pt), and gold (Au), which are named in order of increasing
Anda Yoshiharu
Nishitsuji Mitsuru
Tanaka Tsuyoshi
Ueda Daisuke
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Prenty Mark V.
Studebaker Donald R.
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