Field effect transistor array including refractory metal silicid

Details Field effect transistor array including refractory metal silicid Field effect transistor array including refractory metal silicid

1997-10-30

1999-11-30

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

257211, H01L 27118

Patent

active

059947268

ABSTRACT:
Connection between a PMOS transistor and an NMOS transistor is made through a refractory metal salicide layer in the source and drain regions of these transistors. The salicide is low in resistance, thereby partially substituting for a first Al wiring in intracell wiring. The resulting empty area provides a wiring area and, hence, the freedom of chip layout is enhanced. Besides, in a microcell which constitutes a logic circuit, such as a gate array, lateral wiring grid dots can be utilized as a wiring area.

REFERENCES:
patent: 4750026 (1988-06-01), Kuninobu et al.
patent: 4870300 (1989-09-01), Nakaya et al.
patent: 4923822 (1990-05-01), Wang et al.

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