Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1999-07-12
2001-09-25
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
Reexamination Certificate
active
06294802
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field effect transistor and a method of manufacturing the same and, more particularly, to a high-transconductance, high-performance field effect transistor and a method of manufacturing the same.
2. Description of the Prior Art
FIG. 1
shows the section of one structure of a conventional field effect transistor. As shown in
FIG. 1
, this structure is obtained by sequentially forming a 10-nm thick undoped GaAs buffer layer
32
, a 10-nm thick undoped In
0.25
Ga
0.75
As channel layer
33
, a 25-nm thick Si-doped n-type In
0.48
Ga
0.52
P electron donor layer
34
(n=2×10
18
cm
−3
), and a Si-doped n-type GaAs cap layer
36
(n=2×10
18
cm
−3
) on a GaAs substrate
31
. In this structure, the two-dimensional sheet electron dose and mobility at room temperature are 1.4 to 1.5×10
12
cm
−2
and 7,000 cm
2
/V sec, respectively.
As the gate electrode formation process, a photoresist is applied to an oxide film (Sio
2
), and a pattern is formed by electron beam exposure. A gate pattern is formed on the oxide film by reactive ion etching. Subsequently, using this oxide film as a mask, the GaAs cap layer
36
is etched by selective dry etching to reach the In
0.48
Ga
0.52
P electron donor layer
34
, thereby forming a recess. After that, WSi Schottky gate metal is formed by sputtering, and Au is formed by vapor deposition. Unnecessary gate metal is removed to form a gate electrode.
AuGe/Ni/Au is formed by vapor deposition to form ohmic electrodes, i.e., a source electrode
37
and a drain electrode
38
.
Finally, an SiO
2
/SiN passivation film is formed to obtain a conventional field effect transistor.
According to the characteristics of this conventional field effect transistor, when the transistor has a maximum transconductance gmmax of about 480 mS/mm, a gate-to-drain breakdown voltage BVgd of 7 V or more, and a gate width of 200 &mgr;m, a maximum oscillation frequency fmax is 191 GHz, and a cutoff frequency fT is 76 GHz. These figures are described in IEEE ELECTRON DEVICE LETTERS, VOL. 14, NO. 8, pp. 406-408 (1993).
As a reference that describes conditions for the crystal growth of the conventional field effect transistor described above, Journal of Crystal Growth, vol. 107, pp. 942-946 (1991) is cited. According to this reference, crystal growth is performed by setting the reaction tube pressure to normal pressure and setting the growing temperature to 630° C.
Japanese Unexamined Patent Publication No. 8-306703 and the like describe a compound semiconductor crystal device and a method of manufacturing the same.
The above references concerning the conventional field effect transistor have no description on the direction of the gate finger of the FET and the practical growth conditions for the In
0.48
Ga
0.52
P electron donor layer
34
, which forms an interface together with the In
0.25
Ga
0.75
As channel layer
33
and in which the array of Ga and In layers, i.e., natural superlattice formation state changes depending on the growing temperature, the V/III ratio, the growing rate, and the substrate plane orientation.
In a field effect transistor (FET) using InGaAs as a channel layer, the state of interface between the channel layer and the electron donor layer formed on the channel layer largely affects the mobility of the two-dimensional electron gas. In particular, in an FET having a crystal structure in which InGaP is formed on an InGaAs channel layer as an electron donor layer, the degree of formation of the natural superlattice in the InGaP electron donor layer changes largely depending on the growth conditions for the InGaP crystals. The mobility of the two-dimensional electron gas accordingly changes largely depending on the degree of formation of the natural superlattice.
Depending on the degree of formation of the natural superlattice in the InGaP electron donor layer and the direction of the gate finger, electrons traveling in the channel layer scatter largely to decrease the mobility of the two-dimensional electron gas, and the FET performance that should naturally be obtained cannot be sufficiently obtained.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems in the prior art, and has as its object to provide a high-transconductance, high-performance field effect transistor.
In order to achieve the above object, the field effect transistor according to the present invention has the following arrangement. More specifically, in the field effect transistor according to the present invention, an InGaP electron donor layer which forms a natural superlattice is formed on a (001) surface of a GaAs substrate, and a gate finger is formed to run in a [−110] direction.
The field effect transistor according to the present invention is manufactured in the following manner. More specifically, according to the present invention, there is provided a method of manufacturing a field effect transistor having an InGaAs channel layer and an InGaP electron donor layer on a GaAs substrate, wherein growth conditions for InGaP crystal are set to minimize a band gap energy (energy gap) of the InGaP crystal serving as the electron donor layer to be lattice-matched with the GaAs substrate.
The practical growth conditions for the InGaP crystal are:
the supply amount of a source gas of a Group III element is adjusted to set a growing rate of the InGaP crystal at not more than 0.6 &mgr;m/h;
a ratio of the source gas of a Group V element to the source gas of the Group III element, i.e., a V/III ratio, during growth of the InGaP crystal is set to fall within a range of 400 to 600;
a growing temperature for the InGaP crystal is set to fall within a range of 640° C. to 660° C.; and
a gate finger is formed on a (001) surface of the GaAs substrate to run in a [−110] direction.
Conventionally, among FETs having InGaP formed on their InGaAs channel layer to serve as an electron donor layer, none specifies the state of arrangement of a Group III element of the InGaP crystal.
In the present invention, the InGaP electron donor layer has a crystal structure as described above, and the gate finger is formed to run in the [−110] direction. Hence, electrons in the channel layer travel in the [110] direction, and electrons traveling in the InGaP electron donor layer side of the channel layer scatter less in the interface by the InGaP layer which forms a natural superlattice. Hence, a high-performance FET can be realized.
The above and many other objects, features and advantages of the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principle of the present invention are shown by way of illustrative examples.
REFERENCES:
patent: 5521404 (1996-05-01), Kikkawa et al.
patent: 5751028 (1998-05-01), Kikkawa
patent: 5811844 (1998-09-01), Kuo et al.
patent: 8-306703 (1996-11-01), None
Chaudhuri Olik
Hutchins, Wheeler & Dittmar
NEC Corporation
Wille Douglas A.
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