Field-effect transistor and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor

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257615, H01L 310328

Patent

active

057808791

ABSTRACT:
An FET includes a semi-insulating GaAs substrate, a buffer layer, a first graded layer, a channel layer, a second graded layer, a cap layer, source and drain electrodes, and a gate electrode. The buffer layer consists of a high-resistance semiconductor crystal exhibiting lattice matching with GaAs and is formed on the substrate. The first graded layer consists of an (Al.sub.z Ga.sub.1-z).sub.1-x In.sub.x P semiconductor crystal and is formed on the buffer layer such that the In content is gradually increased with distance from the buffer layer. The channel layer consists of an In.sub.y Ga.sub.1-y As semiconductor crystal and is formed on the graded layer. The second graded layer consists of an (Al.sub.z Ga.sub.1-z).sub.1-x In.sub.x P semiconductor crystal and is formed on the channel layer such that the In content is gradually decreased with distance from the channel layer. The cap layer consists of GaAs and is formed on the second graded layer. The source and drain electrodes are formed on the cap layer. The gate electrode is formed between the source and drain electrodes by removing the cap layer. An Al content z of each graded layer is 0 to 0.5. An In content y of the channel layer is 0.2 to 0.6. A method of manufacturing this FET is also disclosed.

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