Field effect transistor and method of manufacturing the same

Details Field effect transistor and method of manufacturing the same Field effect transistor and method of manufacturing the same

2001-04-03

2003-01-07

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

Diamond or silicon carbide

C257S328000, C257S329000, C257S288000

Reexamination Certificate

active

06504176

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a field effect transistor formed using a wide-gap semiconductor and to a method of manufacturing the same.
2. Related Background Art
Conventionally, various field effect transistors (insulated-gate semiconductor devices) have been proposed. Such field effect transistors (hereinafter also referred to as a “FET”) are required to have a high withstand voltage and low loss.
A conventional FET is described by means of an example as follows.
FIG. 8A
shows a sectional view of a conventional FET
101
formed using Si. The FET
101
includes an n-type substrate
102
, an n-type semiconductor layer
103
grown epitaxially on the substrate
102
, and a p-type region
104
formed by boron implantation in the n-type semiconductor layer
103
. In addition, the FET
101
also includes an n-type region
105
formed by phosphorus implantation in a part of the p-type region
104
in the vicinity of its surface, an insulating layer (a gate insulating layer)
106
formed to cover a portion of the p-type region
104
between the n-type semiconductor layer
103
adjacent to the p-type region
104
and the n-type region
105
, a gate electrode
107
a
formed on the insulating layer
106
, a source electrode
107
b
formed in contact with the p-type region
104
and the n-type region
105
, and a drain electrode
107
c
formed on the rear face of the substrate
102
.
In the FET
101
, a bias is applied to the gate electrode
107
a
, so that an inversion layer is formed in the p-type region
104
and functions as a channel. In the FET
101
, in order to obtain a sufficiently high withstand voltage in an off state, it is necessary to suppress a doping concentration in the n-type semiconductor layer
103
to a low level. This results in higher electrical resistance of the n-type semiconductor layer
103
.
FIG. 8B
shows a sectional view of a conventional FET
101
a
formed using SiC (silicon carbide). With reference to
FIG. 8B
, the FET
101
a
includes an n-type semiconductor layer
103
and a p-type semiconductor layer
109
grown epitaxially by a chemical vapor deposition (CVD) method sequentially-on an n-type substrate
108
made of SiC. In addition, the FET
101
a
also includes an n
+
region
105
a
formed in a part of a surface portion of the p-type semiconductor layer
109
. Thus, the FET
101
a
has an n
+
/p
layered structure. The FET
101
a
includes a trench T passing through the p-type semiconductor layer
109
from the surface of the n
+
region
105
a
and reaching the n-type semiconductor layer
103
. The FET
101
a
is provided with an insulating layer (a gate insulating layer)
106
formed by oxidation of the inner wall of the trench T, a gate electrode
107
a
formed on the insulating layer
106
, a source electrode
107
b
formed in contact with the n
+
region
105
a
and the p-type semiconductor layer
109
, and a drain electrode
107
c
formed on the rear face of the substrate
108
. In the FET
101
a
, a channel region switched on or off depending on a voltage applied to the gate electrode
107
a
is formed in the vicinity of the interface between the p-type semiconductor layer
109
and the insulating layer
106
where the wall surface of the trench T is formed. The details of this conventional technique are disclosed, for example, in Silicon Carbide; A Review of Fundamental Questions and Applications to Current Device Technology, edited by W. J. Choyke, H. Matsunami, and G. Pensl (Akademie Verlag, 1997, Vol. II pp.369-388).
In the FET
101
, the doping concentration and thickness of the n-type semiconductor layer
103
are determined depending on the withstand voltage required for the device. Generally, in order to obtain a withstand voltage of several hundreds of voltages in a Si-MOSFET, the n-type semiconductor layer
103
is required to have a thickness of several tens of micrometers and a low doping concentration of about 10
14
cm
−3
. Therefore, the resistance value in an on state is significantly high. Furthermore, when a thick epitaxial layer is formed at a low doping concentration in the n-type semiconductor layer
103
, there have been problems in that a longer time is required for the formation and the manufacturing cost increases.
The SiC used for the FET
101
a
is a non-isotropic crystal. It has been known that SiC has different oxidation rates depending on crystallographic orientations. A Si plane of an &agr;-SiC(0001) substrate has the lowest oxidation rate. On the contrary, a C plane of an &agr;-SiC(000-1) substrate that is obtained by a 180° rotation of the Si plane has the highest oxidation rate. When an insulating oxidation layer is formed by oxidation of the trench having planes corresponding to a plurality of different crystallographic orientations, the thickness of the insulating oxidation layer thus formed varies depending on the crystallographic orientations. Consequently, the thickness of the insulating silicon oxide layer is not uniform inside the trench and thus a nonuniform electric field is applied to the insulating layer
106
between the gate electrode and the SiC semiconductor. For instance, when the FET
101
a
is formed using the &agr;-SiC(0001) substrate with the Si plane allowing an epitaxial layer with high crystallinity to be obtained, a relatively thin insulating layer
106
is formed on the wafer surface and the bottom surface of the trench T and a relatively thick insulating layer
106
is formed on the wall surface of the trench T as shown in FIG.
8
B. The gate electrode
107
a
also is formed on the surface of the insulating layer
106
formed on the bottom surface of the trench T. As a result, a stronger electric field than that applied to the insulating layer
106
above the channel portion positioned in the vicinity of the wall surface of the trench T is applied to the insulating layer
106
formed on the bottom surface of the trench T. In such a case, the formation of the insulating layer
106
with a sufficient thickness set with consideration given to a withstand voltage for the purpose of forming a field effect transistor with a high withstand voltage results in formation of a very thick insulating layer
106
adjacent to the channel portion (a portion of the semiconductor layer in contact with the wall surface of the trench T). The formation of the thick insulating layer
106
adjacent to the channel portion, however, causes deterioration in the response performance of the device to a gate voltage, and as a result, it is required to apply a high voltage to the gate for on/off switching of the device. When the insulating layer
106
formed adjacent to the channel portion is allowed to have an optimum thickness, there has been a problem in that the thickness of the insulating layer
106
formed on the bottom surface of the trench T is reduced and thus the withstand voltage of this portion decreases. Hence, with the above-mentioned conventional technique, it has been difficult to form a power device with a high withstand voltage and high efficiency using a substrate such as the a-SiC(0001) substrate with a Si plane.
FIG. 9
shows a power MOSFET
200
disclosed in U.S. Pat. No. 5,438,215 to Tihanyi. The FET
200
includes an n-type inner region
201
, a base region
203
, a source region
204
, a drain region
207
, a plurality of p-type additional regions
211
, and n-type additional regions
212
each of which is disposed two adjacent p-type additional regions
211
. The additional regions
212
are doped at a higher concentration than that at which the inner region
201
is doped.
Furthermore, in the case of the FET
200
, in order to form the FET
200
with a withstand voltage of several hundreds of volts to several kilovolts using a semiconductor such as Si, it is necessary to set the length of the additional regions
211
and
212
in the thickness direction A to be several tens of micrometers or longer. In order to form such additional regions
211
and
212
, it is required to repeat epitaxial

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