Field effect transistor and method of fabrication

Details Field effect transistor and method of fabrication Field effect transistor and method of fabrication

2002-11-27

2004-11-30

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

C257S190000, C257S344000, C257S616000

Reexamination Certificate

active

06825506

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuits and more specifically to a depleted substrate transistor (DST) and its method of fabrication.
2. Discussion of Related Art
Modern integrated circuits today are made up of literally hundreds of millions of transistors integrated together into functional circuits. In order to further increase the computational power of logic integrated circuits, the density and performance of the transistors must be further increased and the operating voltage (Vcc) further reduced. In order to increase device performance and reduce operating voltages, silicon on insulator (SOI) transistors have been proposed for the fabrication of modern integrated circuits. Fully depleted SOI transistors have been proposed as transistor structure to take advantage of the ideal subthreshold gradients for optimized on current/off current ratios. That is, an advantage of SOI transistors is that they experience lower leakage currents thereby enabling lower operating voltage for the transistor. Lowering the operating voltage of the transistor enables low power, high performance integrated circuits to be fabricated.
FIG. 1
illustrates a standard fully depleted silicon on insulator (SOI) transistor
100
. SOI transistor
100
includes a single crystalline silicon substrate
102
having an insulating layer
104
, such as buried oxide formed thereon. A single crystalline silicon body
106
is formed on the insulating layer
104
. A gate dielectric layer
108
is formed on a single crystalline silicon body
106
and a gate electrode
110
formed on gate dielectric
108
. Source
112
and drain
114
regions are formed in the silicon body
106
along laterally opposite sides of the gate electrode
110
. Unfortunately, the amount of gate oxide scaling and gate length scaling that can be reliably and uniformly achieved with today's structures and processes is becoming limited.
Thus, what is desired is a novel transistor structure which enables further Vcc scaling and improved electrical performance.


REFERENCES:
patent: 5111255 (1992-05-01), Kiely et al.
patent: 5164797 (1992-11-01), Thornton
patent: 5245208 (1993-09-01), Eimori
patent: 5378923 (1995-01-01), Mitsui et al.
patent: 5430310 (1995-07-01), Shibasaki et al.
patent: 5581092 (1996-12-01), Takemura
patent: 5683934 (1997-11-01), Candelaria
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 5798540 (1998-08-01), Boos et al.
patent: 5986291 (1999-11-01), Currie et al.
patent: 6207977 (2001-03-01), Augusto
patent: 0 531 550 (1993-03-01), None
patent: 1 020 898 (2000-07-01), None
patent: 1 119 029 (2001-07-01), None
patent: 60-251666 (1986-05-01), None
patent: WO 01/88995 (2001-11-01), None
International Search Report PCT/US 03/34667.
Ikeda, K. et al. “50-NM Gate Schottky Source/Drain P-MOSFETS with a SIGE Channel” IEEE Electron Device Letters, IEEE Inc., New York, US, vol. 23, No. 11, Nov. 2002, pp. 670-672, XP001158217, ISSN: 0741-3106, Figure 1.
Chang, C-Y et al. “High Performance Thin-Film Transistors with Low-High-Low Band Gap Engineering”, Proceeding of the SPIE, Bellingham, VA, US, vol. 3421, Jul. 1998, pp. 152-158, XP001189049, ISSN: 0277-786X.

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