Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1999-02-10
2001-08-21
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S279000, C257S284000
Reexamination Certificate
active
06278144
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field-effect transistor and, more particularly, to a field-effect transistor having improved, stabilized off-state breakdown voltage as measured between a gate and a drain, as well as to a method for manufacturing the field-effect transistor.
2. Description of the Related Art
Breakdown voltage is a parameter that determines a maximum output power of a power field-effect transistor (power FET). According to a known method for designing the breakdown voltage of a silicon MOSFET, in which a lightly-doped drain (LDD) region existing between a gate and a drain is regarded a junction FET, the device is considered to have a structure such that a MOSFET and the junction FET are cascode-connected. This idea enables the following design practice for an n-type MOSFET, for example. By adjustment of the dosage of n-type ions implanted into the LDD region existing between a gate and a drain and adjustment of the impurity concentration of a p-type substrate, it becomes possible to arbitrarily choose a design ratio of the voltage applied between the gate and the drain to the voltage applied between the source and the drain. Thus, the on-state breakdown voltage between the source and the drain can be accurately controlled. This technique is described in Proceedings of the 6th Conference on Solid State Devices, p249.
For high power microwave FETs used, for example, in base stations for mobile communications and satellite communications, gallium arsenide (hereinafter abbreviated as GaAs) MESFETs and GaAs heterojunction FETs (HJFETs) have been employed. In contrast to the case of MOSFETs that use a gate insulating film, in these GaAs FETs, a Schottky metal of a gate (hereinafter referred to as a gate metal) exhibits a lower Zener breakdown voltage. Thus, in addition to improvement of off-state breakdown voltage, the on-state breakdown voltage between the gate and the drain must be improved.
FIG. 1
shows a conventional FET in section. According to a known method for improving the on-state breakdown voltage of a GaAs MESFET, an intentionally undoped i-GaAs layer (numeral
44
in
FIG. 1
) is formed as a surface layer of the FET which is in Schottky contact with the gate. This structure improves the maximum reverse breakdown voltage of the gate metal; specifically, the on-state breakdown voltage of the FET is 20 V or higher. This technique is described in IEICE Transactions, Vol. E74, No. 12, 1991.
As an alternative technique, there is widely used an LDD structure in which the impurity concentration of the region existing between a gate and a drain is made lower than that of an ohmic region, as in the case of a MOSFET. In this structure, since the impurity concentration in the vicinity of the gate is lower than that of the ohmic region, electric-field concentration at a gate surface is alleviated. This technique is described in The 17th GaAs IC Symposium, 1995, Technical Digest. By adjustment of the length of the LDD region, a breakdown voltage of 25 V or higher is obtained.
The conventional techniques as described above have provided some advantages, but cannot necessarily exert complete control over the on-state breakdown voltage of GaAs FETs to obtain both the high breakdown voltages. This is because, in the case of GaAs, a high surface state density exists on the surface of a semiconductor, and the surface state density have a great effect on the on-state breakdown voltage, whereas the properties of the surface state density depend on the type of a film and the filming process thereof and are thus difficult to control. In short, the on-state breakdown voltage varies greatly with uncertain factors in a fabrication process, causing frequent occurrence of breakdown defect during fabrication.
Since, in many cases, GaAs FETs employ an epitaxial wafer in which semiconductor layers are grown in the vertical direction, a doping profile cannot be varied parallel to the substrate surface. Thus, application of a cascode connection to a design for a breakdown voltage control as in the case of a silicon MOSFET is difficult in the GaAs FET. Even if an LDD structure is formed in an ordinary GaAs FET by means of ion implantation, the on-state breakdown voltage of the FET is difficult to control, because, in the GaAs FET, dosage of the substrate is usually not controlled for this purpose, and thus, the electric potential of the surface state is unstable.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a field effect transistor having an improved, stable on-state breakdown voltage between gate and source thereof.
It is another object of the present invention to provide a process for fabricating the field effect transistor as mentioned above.
The present invention provides a field effect transistor including a substrate, a first epitaxial layer overlying the substrate and having a first conductivity, a second epitaxial layer formed on the first epitaxial layer and having a second conductivity, source and drain regions in ohmic contact with the second epitaxial layer, and a gate metal formed on the second epitaxial layer in Schottky contact therewith, the second epitaxial layer having an impurity concentration and a thickness such that an electrically neutral region is formed when the gate metal has a potential substantially equal to a potential of the drain region.
The present invention also provides a method for fabricating a field effect transistor including the steps of depositing a first epitaxial layer having a first conductivity and overlying a substrate, depositing a second epitaxial layer having a second conductivity on the first epitaxial layer, forming an ohmic layer on the second epitaxial layer, forming an ohmic layer having a first conductivity on the second epitaxial layer, forming a gate in Schottky contact with the second epitaxial layer and source and drain regions on the ohmic layer, and selectively etching the second epitaxial layer to form an opening for exposing a portion of the first epitaxial layer by using an etchant, the etchant and a semiconductor material of the epitaxial layer being selected such that an etch rate of the second epitaxial layer is lower than an etch rate of the ohmic layer.
In accordance with the field effect transistor of the present invention and fabricated by the method of the present invention, the electrically neutral region functions similarly to the gate of the cascode-connected MOSFET, which improves both the on-state breakdown voltage in the FET.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 4471367 (1984-09-01), Chen et al.
patent: 4636823 (1987-01-01), Margalit et al.
patent: 4839703 (1989-06-01), Ohata et al.
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patent: 4-10440 (1992-01-01), None
patent: 5-275467 (1993-10-01), None
Kunihiro Kazuaki
Ohno Yasuo
Takahashi Yuji
Crane Sara
Hutchins, Wheeler & Dittmar
NEC Corporation
Tran Thien F
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