Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1998-06-11
2001-01-09
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S280000
Reexamination Certificate
active
06172384
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a field effect transistor and a method for manufacturing the same, and especially to a GaAs field effect transistor, which generates high output power and is required to be highly reliable, and a method for manufacturing the same.
BACKGROUND OF THE INVENTION
A GaAs field effect transistor provided with a double recess attracts attentions of electronic engineers as a device, which generates a high output power and withstands a high voltage applied thereto. The double recess is composed of a wide recess and a narrow recess, each having a form of a step of stairs, and formed by etching GaAs in most cases. In order to stabilize the characteristics of the GaAs field effect transistor, it is indispensable to form the wide and narrow recesses with high accuracy. In a method for forming a double recess, which is proposed in a recent year, GaAs active layers and thin AlGaAs etching stopper layers are grown alternately and successively on a GaAs substrate, and the double recess is formed by selectively etching the aforementioned multilayered semiconductor. According to this method, the double recess can be exactly formed because of the presence of the etching stopper layers, and a drain current, a threshold voltage and a gate breakdown voltage of the field effect transistor can be stabilized. However, according to the aforementioned method, a AlGaAs etching stopper layer is exposed on the wide recess. The etching stopper layer is easily oxidized, and surface state levels arise therein, which bring about the fluctuations of the characteristics of the field effect transistors. It is extremely desirable to remove the etching stopper exposed on the wide recess.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a field effect transistor with satisfactory DC and RF performances.
It is a further object of the invention to provide a method for fabricating a field effect transistor with satisfactory and RF performances.
According to the first feature of the invention, a field effect transistor comprises:
a first active layer, a first semiconductor layer and a second active layer successively formed on a substrate,
a narrow recess starting from a top surface of the second active layer and reaching a top surface of the first semiconductor layer,
a second semiconductor layer and a third active layer successively formed on a top surface of the second active layer except a region above the narrow recess,
a wide recess starting from a top surface of the third active layer and reaching the top surface of the second active layer and having a larger aperture area than that of the narrow recess,
a gate electrode formed on a bottom surface of the narrow recess, and
source and drain electrodes respectively formed on the top surface of the third active layer.
According to the second feature of the invention, a method for fabricating a field effect transistor comprises the steps of:
successively growing a first active layer, a first semiconductor layer, a second active layer, a second semiconductor layer and a third active layer on a substrate,
forming a first recess by etching a predetermined part of the third active layer till the second semiconductor layer is exposed,
exposing the second active layer by removing the second semiconductor layer exposed on a bottom surface of the first recess, and
forming a second recess, which has smaller aperture area than that of the first recess, by etching a predetermined part of the second active layer till the first semiconductor layer is exposed.
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Axel H{umlaut over (u)}lsmann, et al., “Fabrication of High Breakdown Pseudomorphic Modulation Doped Field . . . ,” Japenese Journal of Applied Physics, vol. 33, No. 12B, Part 01, pp. 7194-7198, Dec. 1, 1994.
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Foley & Lardner
Meier Stephen D.
NEC Corporation
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