Field effect transistor

Details Field effect transistor Field effect transistor

2005-09-20

2005-09-20

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

C257S183000

Reexamination Certificate

active

06946691

ABSTRACT:
An MESFET is configured wherein a semiconductor layer structure including an i-AlGaAs buffer layer, an n-AlGaAs electron supply layer having an impurity doping density ranging from 1×1017cm−3to 1×1018cm−3and a layer thickness ranging from 1 nm to 10 nm, and an n-GaAs channel layer, all of which are sequentially deposited from the semi-insulating GaAs substrate side, is disposed on the semi-insulating GaAs substrate, a gate electrode is provided on the n-GaAs channel layer, and a source electrode and a drain electrode opposite to each other with the gate electrode interposed therebetween are provided.

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patent: 6365925 (2002-04-01), Hase et al.
patent: 2002/0008249 (2002-01-01), Minetani
patent: 2004/0137673 (2004-07-01), Passlack et al.
R. E. Williams, et al. “Graded Channel FET's: Improved Linearity and Noise Figure”, IEEE Transactions on Electron Devices, vol. ED-25, No. 6, Jun. 1978, pp. 600-605.
James A. Adams, et al. “Short-Channel Effects and Drain-Induced Barrier Lowering in Nanometer-Scale GaAs MESFET's”, IEEE Transactions on Electron Devices, vol. 40, No. 6, Jun. 1993, pp. 1047-1052.

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