Field effect transistor

Details Field effect transistor Field effect transistor

2001-10-30

2003-09-23

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

C257S015000, C257S022000, C257S024000, C257S027000, C257S192000, C257S194000, C257S201000, C257S745000

Reexamination Certificate

active

06624440

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an FET (Field Effect Transistor) and more particularly to a hetero junction FET.
GaAs FETs are extensively used as high frequency devices. As for a high power device, among others, a multi-step recess structure is used to reduce a source resistance and to guarantee a gate breakdown voltage, as taught in, e.g., a paper entitled “High Efficiency Power Module Using HEMT for PDC” presented at the 1996 Conventional of the Electronics Society, the Institute of Electronics and Information Engineers of Japan, Vol. 2, p. 30 (issued Aug. 30, 1996).
On the other hand, ON resistance of an FET, having a multi-step recess structure, is the total distributed equivalent resistance from a source electrode to a drain electrode. A low ON resistance is essential for implementing a desirable power and a desirable efficiency characteristic at low voltage operation. However, an ON resistance available with conventional FETs is high because a contact resistance from a cap layer to a channel layer is high. In addition, sheet resistances at an exposed GaAs layer portion and an exposed AlGaAs gate contact layer portion are high, further increasing the ON resistance.
Technologies relating to the present invention are disclosed in, e.g., Japanese Patent Laid-Open Publication Nos. 4-103136 and 7-335867 and Japanese Patent Application No. 8-288610.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a hetero junction FET having low contact resistance from a cap layer to a channel layer and low resistance at a portion where a GaAs gate buried layer is exposed to the outside.
In accordance with the present invention, in an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on the undoped InGaAs channel layer or the undoped GaAs channel layer, and having a double recess structure formed by using the first and third AlGaAs layers as etching stopper layers, a third AlGaAs layer is doped with a high concentration n-type impurity. A fourth GaAs layer includes an undoped layer contacting the third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming the top of the fourth GaAs layer. The second GaAs gate buried layer and a gate electrode contact each other without any gap.


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Patent Abstracts of Japan, [JP 04 103136], vol. 016, No. 340 (E-1238), Jul. 23, 1992.
Yoshida et al., “High Efficiency Power Module Using HEMT for PDC”, presented at the 1996 Conventional of the Electronics and Information Engineers of Japan, vol. 2, p. 30, (Aug. 1996).

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