Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1999-10-27
2001-12-25
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S024000, C257S201000, C257S214000, C438S172000, C438S167000
Reexamination Certificate
active
06333523
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to structures of field-effect transistor (FET).
2. Related Background Art
As FETs realizing ultrafast operations, there have been known those employing a pulse-doped structure in a channel layer. The pulse-doped structure is a structure in which a channel layer with a high doping concentration is formed directly under an undoped layer (cap layer). The cap layer has a predetermined thickness from the substrate surface on which a gate electrode is formed on the cap layer. FETs having the pulse-doped structure are disclosed, for example, in U.S. Pat. No. 4,163,984 or Japanese Patent Application Laid-Open No. HEI 6-310535.
In n-type FETs having the pulse-doped structure, a long gate effect may occur. The long gate effect is a phenomenon in which, the effective gate length enhances due to a depletion layer on the drain electrode side (where the gate bias is a small negative value). For suppressing the long gate effect, the FET disclosed in Japanese Patent Application Laid-Open No. HEI 4-225533, for example, employs a double-pulse-doped layer structure. The double-pulse-doped layer structure is a structure further comprising a pulse-doped layer (additional doped layer) which is disposed over a channel layer. The channel layer and the additional doped layer are separated from each other by a predetermined distance by an undoped layer (a part of a cap layer). The additional doped layer inhibits the depletion layer from spreading toward the channel layer.
SUMMARY OF THE INVENTION
As a result of studies concerning conventional field-effect transistors, the inventors have found the following problems.
In an FET having the conventional doping configuration, if the bias voltage to the gate electrode is positive, the depletion layer generated may fail to reach the additional doped layer or may not completely deplete the additional doped layer. In such cases, the additional doped layer itself may operate as a current channel together with the channel layer (hereinafter referred to as conductive-channeling of the additional doped layer). The conductive-channeling of the additional doped layer makes it impossible to keep the linearity of mutual conductance g
m
of the FET.
On the other hand, the drain breakdown voltage of FET strongly depends on the distance between the gate electrode and the channel layer. If the distance between the gate electrode and the channel layer is enhanced in order to improve the drain breakdown voltage, then the conductive-channeling of the additional doped layer becomes particularly influenced.
An object of the present invention is to provide a field-effect transistor comprising a structure which improves the linearity of mutual conductance g
m
.
The field-effect transistor of the present invention comprises a channel layer disposed on a substrate, an auxiliary region disposed on the channel layer, and a cap layer disposed on the auxiliary region. A gate electrode is disposed on the cap layer. The channel layer is disposed at a position separated from the gate electrode by at least 600 angstroms.
The auxiliary region is positioned between the cap layer and the channel layer, and has an upper interface directly in contact with the cap layer and a lower interface directly in contact with the channel layer. The auxiliary region has a doping concentration lower than that of the channel layer and higher than that of the cap layer.
The auxiliary region comprises one or more auxiliary layers each having a conductivity type identical to that of the channel layer. The doping concentration of the one or more auxiliary layers may be set such that the doping profile of a laminated structure constituted by the channel layer, the one or more auxiliary layers, and the cap layer exponentially lowers from the channel layer toward the cap layer.
The existence of the auxiliary layers inhibits the depletion layer from spreading to the channel layer (suppresses the long gate effect and the like). Since the channel layer and the auxiliary layer are directly in contact with each other, only the channel layer acts as a current channel even in the case where the gate bias is positive or small negative. These characteristics improve the linearity of mutual conductance g
m
over a wide range of gate bias. In particular, increasing the number of auxiliary layers enables a high linearity in mutual conductance g
m
.
As the cap layer is further provided on one or more auxiliary layers, a planar type field-effect transistor having a high drain breakdown voltage is obtained.
The doping concentrations of the channel layer, one or more auxiliary layers, and cap layer, with respect to the distance x along an axis directed from the gate electrode to the channel layer, substantially coincide with the following exponential function:
N=A exp(&agr;x)
where A and &agr; are constants.
When the function indicative of the decrease in doping concentration of each layer is made to approximately coincide with an exponential function, the linearity in mutual conductance g
m
improves in particular.
The present invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only and are not to be considered as limiting the present invention.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will be apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5493136 (1996-02-01), Matsuzaki et al.
patent: 6049097 (2000-04-01), Hida
patent: 6064082 (2000-05-01), Kawai et al.
patent: 6121641 (2000-09-01), Ohno
patent: 6144048 (2000-11-01), Suemitsu et al.
patent: 6147370 (2000-11-01), Kanamori
patent: 6180968 (2001-01-01), Kasahara et al.
patent: 6184546 (2001-02-01), Liu et al.
patent: 6184547 (2001-02-01), Onda
patent: 6194747 (2001-02-01), Onda
patent: 6201267 (2001-03-01), Gupta et al.
patent: 6255673 (2001-07-01), Kuzuhara
patent: 6262444 (2001-07-01), Hori et al.
patent: 6274893 (2001-08-01), Igarashi et al.
patent: 4-101436 (1992-04-01), None
Article entitled “GaAs FETs With Graded Channel Doping Profiles”, from Electronics Letters, XP002128687; pp. 408-409, by R. Willaims et al., (1977).
Article entitled “X-Band Monolithic Four-Stage LNA with Pulse-Doped GAAS Mesfets”, USA Technical Digest, Oct. 1999; pp. 237-240, by Shiga et al.
Hashinaga Tatsuya
Sakamoto Ryoji
Luu Chuong A
Smith Matthew
Smith , Gambrell & Russell, LLP
Sumitomo Electric Industries Ltd.
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