Field effect transistor

Details Field effect transistor Field effect transistor

1999-06-11

2001-12-11

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

C257S408000

Reexamination Certificate

active

06329677

ABSTRACT:

This application is based on Japanese patent application HEI 10-317940 filed on Nov. 9, 1998, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a field effect transistor and its manufacture, and more particularly to a field effect transistor capable of having a sufficiently high gate breakdown voltage and a low source resistance and to its manufacture.
b) Description of the Related Art
A field effect transistor has a source electrode, a gate electrode and a drain electrode on a semiconductor active region with a channel region. A gate voltage applied to the gate electrode controls current flowing through the source-drain electrodes. In most of field effect transistors made of compound semiconductor, the source and drain electrodes have ohmic contacts on the semiconductor surface in the active region and the gate electrode has a Schottky contact on the semiconductor surface in the active region. Such a field effect transistor made of compound semiconductor will be described hereinunder.
In a field effect transistor having a Schottky gate electrode, leak current is likely to flow between the gate electrode and the ohmic source-drain electrodes. In order to increase the conductivity of the channel region, a forward voltage is applied to the gate electrode. The forward voltage is a voltage having a polarity opposite to that of carriers to be transferred, e.g., a positive voltage if an n-channel transistor is used. A forward gate breakdown voltage is represented by Vf when the forward voltage is applied. In order to extinguish the conductivity of the channel region, a reverse voltage is often applied to the gate electrode, e.g., a negative voltage if an n-channel transistor is used. The reverse gate breakdown voltage is represented by Vr when the reverse voltage is applied.
If a normally-on type field effect transistor whose channel region is normally on is used, only a reverse voltage may be applied to the gate electrode. However, if the conductivity of the channel region is to be improved, it is desired to apply a forward voltage to the gate electrode.
If a normally-off type field effect transistor whose channel region is normally off is used, only a forward voltage may be applied to the gate electrode to turn on the channel region. However, if the off-state is to be made more stable, it is desired to apply a reverse voltage to the gate electrode. It is therefore desired that both the forward and reverse breakdown voltages Vf and Vr are high.
In order to increase a saturation current Imax of a field effect transistor, it is desired that the resistance of a current path between the source-drain electrodes is low. A depletion layer is often formed in the current path between the gate electrode and the drain electrode. In such a case, the resistance of the current path is mainly governed by the resistance between the source electrode and the channel region under the gate electrode, i.e., a source resistance Rs. In order to increase the saturation current Imax by reducing the source resistance, it is desired to lower the resistance between the channel region which is controlled by the potential of the gate electrode and the source region under the source electrode which has generally a high impurity concentration.
Generally, a field effect transistor is often operated by exchanging the functions of the source and drain electrodes. To satisfy such requirements, a field effect transistor is designed to have the source and drain electrodes disposed symmetrically with the gate electrode, so that the same transistor performance can be obtained even if the functions of the source and drain electrodes are exchanged. The source electrode can therefore be used as the drain electrode, and vice versa.
As a method of lowering the source resistance Rs in order to increase the saturation current Imax, impurity ions are implanted into the semiconductor region between the gate electrode and ohmic electrode and activated to increase the conductivity. This structure is, however, likely to increase the leak current between the gate electrode and ohmic electrode and lower the gate breakdown voltages Vf and Vr.
Another method of lowering the source resistance Rs is to shorten the distance between the gate electrode and ohmic electrode. However, the short distance between the gate electrode and ohmic electrode is also likely to lower the gate breakdown voltages Vf and Vr.
Reducing the source resistance Rs and keeping the gate breakdown voltages Vf and Vr are more or less contradictory, and it is difficult to satisfy both the requirements.
The source resistance of a field effect transistor having a Schottky gate electrode is difficult to be lowered while the gate breakdown voltages are maintained high.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a field effect transistor capable of lowering the source resistance while the gate breakdown voltages are maintained sufficiently high.
According to one aspect of the present invention, there is provided a field effect transistor comprising: a semiconductor lamination structure having a principal surface; a gate electrode disposed on the principal surface and forming a Schottky contact with the principal surface;a pair of source/drain electrodes disposed on the principal surface on both sides of the gate electrode and each forming an ohmic contact with the principal surface; a pair of source/drain regions disposed in the semiconductor lamination structure under the pair of source/drain electrodes and each forming a current deriving region; a channel layer disposed in the semiconductor lamination structure spaced apart from the principal surface and disposed to be connected to the pair of source/drain regions;a barrier layer disposed in the semiconductor lamination structure between the channel layer and the principal surface and having a conduction band edge energy higher than a conduction band edge energy of the channel layer; and a pair of impurity doped regions formed in the barrier layer and the channel layer continuously with the pair of source/drain regions on both sides of the gate electrode, a carrier density in the barrier layer being lower than a carrier density in the channel layer, in the pair of impurity doped regions.
According to another aspect of the present invention, there is provided a method of manufacturing a field effect transistor comprising the steps of: preparing a lamination substrate having a lamination structure formed on a semiconductor substrate, the lamination structure including a channel layer having a first conduction band edge energy and a barrier layer formed on the channel layer, the barrier layer having a second conduction band edge energy higher than the first conduction band edge energy; forming a gate electrode on a surface of the lamination structure of the lamination substrate; doping impurities into the lamination structure in intermediate regions on both sides of the gate electrode; and activating the impurities under conditions that a first carrier density in the channel layer becomes higher than a second carrier density in the barrier layer.
The lamination structure of a channel layer and a barrier layer is formed in an active region, and in the regions on both sides of the gate electrode, the channel region is formed to have a relatively high carrier density and the barrier layer is formed to have a relatively low carrier density. In this manner, a low source resistance can be realized while the gate breakdown voltage is maintained high.
As above, in a region between the source/drain regions below the gate electrode, a high resistivity barrier layer is maintained, while a low resistivity region is formed under the barrier layer, extending toward the gate electrode from the source/drain region. The source resistance can therefore be lowered while the gate breakdown voltages are maintained high.


REFERENCES:
patent: 5831306 (1998-11-01), Gardner et al.
patent: 6020604 (2000-02-01), Ki

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