Field effect transistor

Details Field effect transistor Field effect transistor

1999-03-12

2001-09-18

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

Reexamination Certificate

active

06291842

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an FET (Field Effect Transistor) and more particularly to an FET having a high cutoff frequency.
To enhance the high frequency characteristic of an InAlAs/InGaAs FET formed on a substrate, it has been customary to provide an InGaAs layer or operating layer (carrier running layer) with a high InAs composition ratio. The effective InAs composition ratio of the operating layer may be increased by, e. g., inserting an InAs layer in an In
0.53
Ga
0.47
As operating layer to form an In
0.53
Ga
0.41
As/InAs/In
0.53
Ga
0.47
As structure, as proposed by Akasaki et al. in IEEE ELECTRON DEVICE LETTERS, VOL. 13, NO. 6, pp. 325, JUNE 1992.
The FET structure taught in the above document includes a substrate. Sequentially formed on the substrate are an InAIAs buffer layer, an InGaAs operating layer with an InAs layer inserted therein, an InAlAs spacer layer, an n-InAlAs carrier supply layer with Si added thereto, an InAlAs gate Schottky layer, an n-InAlAs cap layer with Si added thereto, and an n-In-GaAs cap layer with Si added thereto. The two cap layers and Schottky layer are partly removed by recess etching. Subsequently, a source and a drain electrode are formed on the n-InGaAs cap layer while a gate electrode is formed on the Schottky layer. The document describes that the above structure improves an electron transport characteristic, compared to a structure lacking the InAs layer in the InGaAs operating layer.
However, Akasaki et al. report that mobility decreases when the thickness of the InAs layer exceeds 4 nm. Because the InAs layer has a distortion of about 3.2% with respect to the substrate, a thickness insuring desirable crystal structure, i.e., a critical thickness is considered to be about 4 nm. As for the critical thickness, estimation based on, e.g., the theory of J. W. Matthews et al. disclosed in Journal of Crystal Growth, VOL. 27, pp. 118, 1974 also indicates that the critical thickness of InAs layer with respect to the substrate and InGaAs layer or the InAlAs layer lattice-matched to the substrate is about 4 nm. That is, the thickness of the InAs layer exceeding 4 nm deteriorates the crystal structure and electron transport characteristic. Therefore, with the conventional technologies, it is impossible to implement an InAs layer thicker than 4 nm as the operating layer of an FET. Moreover, when the InAs layer is thinner than 4 nm inclusive, electrons penetrate into the In
0.53
Ga
0.
47
As layer inferior in electron transport characteristic to the InAs layer adjoining it and run through both of the InAs layer and InGaAs layer. It is therefore impracticable to make the most of the desirable electron transport characteristic of the InAs layer or to enhance the characteristic of the FET to a sufficient degree.
Technologies relating to the present invention are also disclosed in Japanese Patent Laid-Open Publication Nos. 5-175246, 6-163601, 8-181304, and 9-172164.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an FET capable of suppressing the penetration of carriers from an InAs operating layer to thereby enhance the confinement of the carriers in the operating layer, and obviating the deterioration of a crystal structure and that of the carrier transport characteristic ascribable thereto to thereby provide the InAs layer with an unprecedented carrier transport characteristic.
In accordance with the present invention, in a hetero junction FET formed on a high resistance substrate and including an InAs layer in a carrier running layer, the InAs layer is thicker than 4 nm, and a layer of AlAs or GaAs or a mixture thereof is formed on and contacts the InAs layer.


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patent: 5756375 (1998-05-01), Celii et al.
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patent: 4-333242 (1992-11-01), None
patent: 9-175240 (1993-07-01), None
patent: 5-175246 (1993-07-01), None
patent: 05175246 A (1993-07-01), None
patent: 6-163601 (1994-06-01), None
patent: 8-181304 (1996-07-01), None
Akazaki et al., “Improved InAIAs/InGaAs HEMT Charactistics by Inserting an InAs Layer into the InGaAs channel”, IEEE Elec. Dev. Lett. V13, pp325-327, Jun. 1992.*
Tatsushi AKAZAKI et al, “Improved InAIAs/InGaAs HEMT Characteristics by Inserting an InAs Layer into the InGaAs Channel”, IEEE Electronic Device Letters, vol. 15, No. 6, Jun. 1992, pp. 325-327.

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