Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – With means to prevent contact from penetrating shallow pn...
Patent
1989-01-23
1993-08-10
Wojciechowicz, Edward
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
With means to prevent contact from penetrating shallow pn...
257279, 257281, 257289, 257769, 257773, H01L 2348
Patent
active
052352102
ABSTRACT:
An SB FET comprising source and drain regions formed in the surface of a gallium arsenide (GaAs) substrate, and a channel region formed between the source and drain regions. The gate electrode of the SB FET is formed on the channel region in Schottky contact therewith. The SB FET further comprises source and drain electrodes which are mounted on the source and drain regions in ohmic contact therewith, while being separated from each other at a greater distance than the length of the channel region.
REFERENCES:
patent: 4310570 (1982-01-01), Calviello
patent: 4375643 (1983-03-01), Yeh et al.
patent: 4393578 (1983-07-01), Cady et al.
patent: 4397075 (1983-09-01), Fatula et al.
Translation of the portion of Japanese Patent (Kokoku) No. 58-53516 describing FIGS. 2 to 4.
Kabushiki Kaisha Toshiba
Wojciechowicz Edward
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