Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Patent
1998-02-02
2000-11-07
Guay, John
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
257778, H01L 29778
Patent
active
061440493
ABSTRACT:
There is provided a field effect transistor including a semi-insulating semiconductor substrate formed with a recess at a region in which a gate is to be formed, a gate base layer formed on the recess and composed of one of an InP layer and a plurality of layers including an InP layer, and a gate electrode formed on the gate base layer. The InP layer may be replaced with an InGaP layer, an Al.sub.X Ga.sub.1-X As (0.ltoreq.X.ltoreq.1) layer, an In.sub.X Ga.sub.1-X As (0.ltoreq.X.ltoreq.1) layer, or an In.sub.X Al.sub.1-X As (0.ltoreq.X<0.4 or 0.6<X.ltoreq.1) layer. The above-mentioned field effect transistor prevents thermal instability thereof caused by impurities such as fluorine entering a donor layer to thereby inactivate donor. As a result, there is presented a highly reliable compound field effect transistor.
REFERENCES:
patent: 4814836 (1989-03-01), Thompson
patent: 5811843 (1998-09-01), Yamamoto et al.
K.H.G. Duh et al., IEEE Microwave and Guided Wave Letters, vol. 1, No. 5, "A Super Low-Noise 0.1 .mu.m T-Gate InAlAs-InGaAs-InP HEMT", May 1991, pp. 114-116.
G.I. Ng. Dimitrios Pavlidis et al., IEEE Electron Device Letters, vol. 10, No. 3, "Improved Strained HEMT Characteristics Using Double-Heterojunction In.sub.0.65 Ga.sub.0.35 As/In.sub.0.52 Al.sub.0.48 As Design", Mar. 1989, pp. 114-116.
N. Hayafuji et al., Applied Physics Letters, vol. 66, No. 7, "Thermal Stability of AIInAs/GaInAs/InP. Heterostructures", Feb. 1995, pp. 863-865.
N. Takahashi et al., Proceedings of 7th International Conference of InP and Related Materials, "Thermal Stability of AI.sub.0.48 In.sub.0.52 As/Ga.sub.0.47 In.sub.0.53 As/InP Heterostructure and Its Improvement by Phosphidization", 1995, pp. 597-600.
A. Fujihara et al., Technical Report of IEICE "Thermal Stability of InAIAs/InGaAs HJFETs with an In(AI.sub.1-x Ga.sub.x)As Layer", pp. 13-20.
A. Fujihara et al., Electronic Letters, vol. 32, No. 11, "Thermally Stable InAIAs/InGaAs Heterojunction FET with AIAs/InAs Superlattice Insertion Layer", May 23, 1996, pp. 1039-1041.
Takatomo Enoki et al., Proceeding of 7th International Conference of InP and Related Materials, "0.1 .mu.m InAIAs/InGaAs HEMTS With an InP-Recess-Etch Stopper Grown by MOCVD", 1995, pp. 81-84.
A. Mesquida Kusters et al., IEEE Electron Device Letters, vol. 16, No. 9, "Sub-Half-Micrometer Pseudomorphic InP/In.sub.x Ga.sub.1-x As/InP HEMT's (0.74.ltoreq..times..ltoreq.0.81) with Very High f.sub.T Values", Sep. 1995, pp. 396-398.
A. Mesquida Kusters et al., IEEE Electron Device Letters, vol. 14, No. 1, "Double-Heterojuntion Lattice-Matched and Pseudomorphic InGaAs HEMT with .delta.-Doped InP Supply Layers and p-InP Barrier Enhancement Layer Grown By LP-MOVPE", Jan. 1993, pp. 36-39.
Guay John
NEC Corporation
LandOfFree
Field effect transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Field effect transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Field effect transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1643670