Field effect transistor

Details Field effect transistor Field effect transistor

1996-11-04

1997-10-14

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257754, 257773, H01L 2943

Patent

active

056775733

ABSTRACT:
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.

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T.Y. Hsieh et al., "Silicon Homoepitaxy by Rapid Thermal Processing Chemical Vapor Deposition (RTPCVD)--A Review", J. Electrochem. Soc., vol. 138, No. 4, Apr. 1991, pp. 1188-1207.
Rahat, Ido et al., "Reducing the Temperature of Conventional Silicon Epitaxy for Selective Poly-Epi Growth", J. Electrochem. Soc., vol. 138, No. 8, Aug. 1991, pp. 2370-2374.
Mazure, Carlos et al., "Facet Engineered Elevated Source/Drain By Selective Si Epitaxy For 0.35 Micron MOSFETS", IEDM, 1992, pp. 853-856.

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