Field effect transistor

Details Field effect transistor Field effect transistor

1995-02-07

1996-01-23

Fahmy, Wael M.

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

257194, 257279, 257284, H01L 310328, H01L 2980, H01L 31112

Patent

active

054867100

ABSTRACT:
A field effect transistor includes a semi-insulating GaAs substrate; source, gate, and drain electrodes disposed on a surface of the GaAs substrate; a low carrier concentration active region disposed in the GaAs substrate lying beneath the gate electrode; intermediate carrier concentration regions disposed in the GaAs substrate at opposite sides of and in contact with the low carrier concentration active region; high carrier concentration source and drain regions disposed in the GaAs substrate at opposite sides of and in contact with the intermediate carrier concentration regions and lying beneath the source and drain electrodes, respectively; and first and second high carrier concentration regions having a carrier concentration as high as or higher than that of the high carrier concentration source and drain regions. The first and second high carrier concentration regions are disposed in the intermediate carrier concentration regions and reach the surface. In this structure, extension of a surface depletion layer in the vicinity of the gate is restricted to the first and second high carrier concentration regions, so that the depletion layer and surface levels do not adversely affect device characteristics.

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H. M. Macksey, "GaAs Power FET's . . . than the Gate", IEEE Electron Device Letters, vol. EDL-7, No. 2, Feb. 1986, pp. 69 & 70.
Hagio et al., "A New Self-Align . . . Analog MMIC's", IEEE Electron Devices, vol. ED-33, No. 6, Jun. 1986, pp. 754-758.
Ito et al., "A Self-Aligned Planar . . . for MMICs", IEEE GaAs IC Symposium, pp. 45-48.
R. Yeats et al., "Gate Slow Transients in GaAs MESFETs . . . Impact on Circuits", IEDM (International Electron Devices meeting), pp. 842-846.
Canfield et al, "Suppression Of Drain Conductance Transients, Drain Current Oscillations, And Low-Frequency Generation-Recombination Noise In GaAs FET's Using Buried Channels", IEEE Transactions on Electron Devices, vol. ED-3, No. 7, Jul. 1986, pp. 925-928.

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