Field-effect transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor

Reexamination Certificate

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Details

C257S194000, C257SE29120, C257SE29246

Reexamination Certificate

active

11189842

ABSTRACT:
The present invention, which aims to provide a gallium arsenide field-effect transistor that can reduce degradation of field-effect transistor characteristics, and to realize miniaturization of the transistor, includes: a substrate; a mesa which includes a channel layer and is formed on the substrate; a source electrode formed on the mesa; a drain electrode; and a gate electrode, wherein, on the mesa, a top pattern is formed in which finger portions of the source electrode and the drain electrode which are formed in comb-shape are located so as to interdigitate, and a gate electrode is formed between the source electrode and the drain electrode, while common portions, which are base parts of the finger portions of the source and drain electrodes, are formed on the surface of the mesa, and the part located below the straight portion which is parallel to the finger portions of the gate electrode is electrically separated from the part located below a corner portion that connects neighboring straight portions of the gate electrode.

REFERENCES:
patent: 4462041 (1984-07-01), Glenn
patent: 6940705 (2005-09-01), Yeo et al.
patent: 2005/0116253 (2005-06-01), Yamane et al.
patent: 2110943 (1990-04-01), None
patent: 5251479 (1993-09-01), None
patent: 6163604 (1994-06-01), None
patent: 2005-072671 (2005-03-01), None
U.S. Appl. No. 11/127,178, filed May 12, 2005.
English Language abstract of JP-6-163604, Nov. 26, 1992.
English Language abstract of JP-2005-72671, Aug. 27, 2003.
English Language abstract of JP-2-110943, Oct. 19, 1988.
English Language abstract of JP-5-251479, Nov. 27, 1991.

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