Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1998-07-10
2001-07-17
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S194000, C257S195000, C438S172000
Reexamination Certificate
active
06262444
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a compound semiconductor field effect transistor and a manufacturing process thereof in which the cap layer for contact resistance reduction has a recess structure, and more specifically, a field effect transistor and a manufacturing process thereof for achieving high breakdown voltage.
2. Description of the Related Art
In the case of a field effect transistor (FET) with a recess structure, electrons are trapped on the surface by forming the passivation film or carrying out functions as FET, and the electric field concentrated portion moves from the drain edge of the gate to the recess edge on the drain side with a sharp angle. In the field effect transistor, there are avalanche effect and tunnel current from the electric field concentrated portion for factors to determine the reverse breakdown voltage characteristics between gate and drain. Consequently, in the case of the field effect transistor with a recess structure, the reverse breakdown voltage value is restricted by the recess edge, that is, the recess profile.
FIG. 1
is a schematic cross-sectional view showing the construction of the heterostructure FET of conventional FETs which have the GaAs cap layer. In
FIG. 1
, on the semi-insulating GaAs substrate
171
, undoped GaAs buffer layer
172
, undoped Al
0.3
Ga
0.7
As heterostructure buffer layer
173
, undoped GaAs channel layer
174
, impurity doped Al
0.3
Ga
0.7
As donor layer
175
, and impurity doped GaAs contact resistance reducing cap layer
176
are laminated successively by the epitaxial growth process. And the impurity doped GaAs contact resistance reducing cap layer
176
is shaved by recess-etching, and thereafter, a gate electrode
177
is formed on the impurity doped Al
0.3
Ga
0.7
As donor layer
175
, and source and drain electrodes
178
,
179
are formed on the cap layer
176
.
FIG. 2
shows the potential distribution when voltage is applied to the conventional FET, while
FIG. 3
shows the voltage resistance characteristics. In general, when the passivation film is formed, or functions as FET are being carried out, it is known that electrons are trapped on the semiconductor surface or semiconductor/passivation film interface. It is known that by this electron capture, the potential which has the surface condition liable to be influenced changes and the electric field concentrated portion moves not to the gate edge between the gate and the drain but to the drain side.
As shown in
FIG. 2
, the potential distribution
810
moved to the drain side is concentrated to the recess edge on the drain side with an obtuse angle or acute angle formed from the surface of the impurity doped Al
0.3
Ga
0.7
As donor layer
175
to which the gate electrode is arranged and the side of the impurity doped GaAs contact resistance reducing cap layer
176
. Consequently, the reverse breakdown voltage value that serves as a major factor for determining the potential distribution is determined on the recess edge on the drain side.
However, since in the FET shown in
FIGS. 1 through 3
, the recess edge on the drain side has either an acute or obtuse profile, the electric field distribution moved to the drain side is concentrated at the recess edge with this angle. Consequently, avalanche yield occurs at this recess edge and the reverse breakdown voltage value is determined. That is, the conventional FET has a problem of restricting the breakdown voltage characteristics by the recess edge on the drain side with the angle formed from the semiconductor surface which comes in contact with the side surface of the contact resistance reducing cap layer at the gate electrode. In addition, carrying out equivalent etching at both edges of the drain side and the source side increases resistance on the source side, and as a result, FET characteristics may be degraded.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a field effect transistor and the manufacturing process thereof, which can alleviate the concentration of the electric field caused by the recess edge profile, that is, restrict the avalanche yield, and improve the breakdown voltage characteristics without degrading the source resistance by making the recess profile a gently curvilinear form and eliminating angles, particularly by making the recess profile on the drain side to which the electric field is applied a gently curvilinear form and eliminating angles as compared to the recess profile on the source side.
In this invention, because the recess edge profile has angles which result in the concentration of an electric field, when the cross section is seen in
FIG. 1
, as a contact resistance reducing cap layer that forms a recess in a recess structure type compound semiconductor, it is an important objective of this invention to make the recess have a profile for avoiding the concentration; that is, the object can be achieved by making the recess profile curvilinear. A specific method to achieve this construction is to use a layer which has a composition subject to etching at least from the bottom portion towards the surface side for a contact resistance reducing cap layer, which is etched in the recess etching process, and for example, as one embodiment, the In composition is increased from the relevant contact resistance reducing cap layer bottom portion towards the surface side, the In graded layer in which the In composition is reduced again or the InGaAs layer in which the In composition varies stepwise is further formed by an epitaxial process or In ion implantation near the top layer as required, and the In graded layer has the recess edge formed curvilinearly using selective etching with a higher etching rate on InAs than on GaAs.
In this invention, for example, for a contact resistance reducing cap layer that forms the recess profile in the recess structure type compound semiconductor, the In composition is increased from the bottom portion of the relevant contact resistance reducing cap layer towards the surface side, and the In graded layer in which the In composition is reduced again or an InGaAs layer in which the In composition varies stepwise is formed by the epitaxial process or by In ion implantation in the vicinity of the top most surface. In addition, using selective etching which provides higher etching rate on InAs than on GaAs, the InGaAs contact resistance reducing cap layer can have the recess edge comprising a flat surface without acute or obtuse angles easily in the etching process, for example, only one etching process. As a result, because the recess edge angle on the drain side to which the electric field is concentrated can be eliminated, the high-breakdown voltage characteristics can be improved without having the reverse high-breakdown voltage value restricted by the recess profile.
In this invention, a recess profile which gently curves on the drain side as compared to the source side by one etching process through ion-implanting, for example, In once or in several portions into the contact resistance reducing cap layer that forms the recess profile in, for example, recess structure compound semiconductor. That is, by using the selective etching with a higher etching rate on InAs than on GaAs, the GaAs contact resistance reducing cap layer with this In ion implantation applied can be formed in a curvilinear profile comprising a flat recess edge free of acute or obtuse angles easily in one etching process. As a result, since the angle of the recess edge on the drain side to which the electric field is concentrated, the breakdown voltage characteristics can be improved without restricting the reverse breakdown voltage value due to the recess profile. In addition, because on the source side, the profile is not so much hollowed out than that on the drain side, it is possible to suppress degradation of the source resistance.
REFERENCES:
patent: 4952527 (1990-08-01), Calawa et al.
patent: 5250822 (1993-10-01), Sonoda et al.
patent: 5391899 (1995-02-01), Kohno
patent: 5486710 (1996-01-01
Hori Yasuko
Onda Kazuhiko
Mintel William
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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