Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Patent
1993-08-20
1995-04-04
Prenty, Mark V.
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
257191, 257194, 257615, H01L 29161, H01L 2980
Patent
active
054040329
ABSTRACT:
A novel field-effect semiconductor device having both low-noise and high-output operating characteristics has a first semiconductor buffer layer, an undoped second semi-conductor layer, an undoped third semiconductor layer the forbidden band gap of which increases from the substrate to the electrode side, a fourth semiconductor layer of one conductivity type, and a fifth semiconductor layer of undoped type or one conductivity type, formed one on top of another in this order on a semiconductor substrate. When the gate potential is deep, electrons mostly travel through the undoped second and third semiconductor layers, the device exhibiting superior low-noise characteristic; when the gate potential is shallow, electrons mostly travel through the highly doped fourth semiconductor layer, the device thus achieving high output characteristic.
REFERENCES:
patent: 5091759 (1992-02-01), Shih et al.
patent: 5099295 (1992-03-01), Ogawa
patent: 5206527 (1993-04-01), Kuwata
"The Backside Pulse Doped Channel Heterostructure Field-Effect Transistor: Design, DC, and RF Performance"-Jpn. J. Appl. Phys. vol. 32 (1993) pp. 17-25 Part 1, No. 1A, Jan. 1993.
"Very High Power-Added Efficiency and Low-Noise 0.15-.mu.m Gate-Length Pseudomorphic HEMT's"-IEEE Electron Device Letters, vol. 10, No. 12, Dec. 1989.
"Low-Noise Characteristics of Pulse-Doped GaAs MESFET's with Planar Self-Aligned Gates"-IEEE Transactions On Electron Devices. vol. 39, No. 4, Apr. 1992.
Harada Yasoo
Sawada Minoru
Prenty Mark V.
Sanyo Electric Co,. Ltd.
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