Field effect level sensitive circuit

Details Field effect level sensitive circuit Field effect level sensitive circuit

1982-02-05

1984-06-26

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307358, 365104, 365208, H03K 3023, H03K 3353, G01R 19165, G11C 706

Patent

active

044568410

ABSTRACT:
A level sensitive switching circuit particularly useful as a data detecting sense amplifier for a Read-Only Memory integrated circuit. The switching circuit includes a pair of IGFET inverter circuits coupled between a drain supply voltage and a common voltage node. The signal to be sensed is applied to the input of the first inverter, the output of which is the circuit output. Two feedback loops are established between the output of the first inverter and the source electrode of an IGFET input device in the first inverter. The first feedback loop includes a source follower responsive to the output of the first inverter and the second feedback loop includes the second inverter having its output coupled to the gate of one of two series-connected devices between the common voltage node and the source supply voltage. The other series-connected device is responsive to an amplifier set clock pulse to selectively enable the circuit.

REFERENCES:
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patent: 4048524 (1977-09-01), Laugesen et al.
patent: 4063119 (1977-12-01), Odell et al.
patent: 4071784 (1978-01-01), Maeder et al.
patent: 4242604 (1980-12-01), Smith
patent: 4274147 (1981-06-01), Padgett et al.
patent: 4375039 (1983-02-01), Yamauchi
K. Kiuchi et al., "A 65 mW 128K EB-ROM", IEEE Journal of Solid-State Circuits, vol. SC-14, No. 5, Oct. 1979, pp. 855-859.
Y. Kitano et al., "A 4-Mbit Full-Wafer ROM", IEEE Journal of Solid-State Circuits, vol. SC-15, No. 4, Aug. 1980, pp. 686-693.
H. Kalter et al., "High Noise Immunity Column . . . ", IBM Technical Disclosure Bulletin, vol. 23, No. 6, Nov. 1980, pp. 2250-2254.

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