Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2000-12-08
2002-07-23
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S139000, C257S133000, C257S110000, C257S147000, C257S134000
Reexamination Certificate
active
06423986
ABSTRACT:
TECHNICAL FIELD
This invention relates to power semiconductor devices, and more particularly relates to power semiconductor devices in which a p-n junction, remote from the device surfaces, carries the device operating voltage and field effect gates are used to control the device operation.
BACKGROUND ART
Power semiconductors, as distinguished from signal semiconductors, are used to process and control the flow of electric energy supplied to user loads. The utility of such devices is driven by their ability to quickly and efficiently switch on and off large operating voltages and currents. Power semiconductor switching devices are increasingly being designed to handle applications requiring high blocking voltages in the off condition, typically 1 kV and greater, and high current requirements in the on state, typically 1 A and greater. Recent advances in device operating thresholds, however, have imposed operational and fabrication-related problems for power semiconductor devices.
Historically, power semiconductor devices have required large switching currents to handle the corresponding high device currents. Large switching currents result in device inefficiencies since excessive electrical power is required to operate the device. Power semiconductor devices to-date have employed metal-oxide-semiconductor (MOS) gate structures in a variety of arrangements to achieve the low current turn-on and turn-off requirements of these devices. However, MOS gates have experienced operational and fabrication-related reliability problems as the operational boundaries of the power semiconductor devices have been expanded. In particular, the high operating device voltages create large electric fields within these devices, which poses long-term reliability problems for the oxides used in the MOS gates. Trenched MOS gates (UMOS), as found in the paper by A. K. Agarwal et al. entitled SiC Power Device Development given at the All Electric Combat Vehicle (AECV) Second International Conference Jun. 8th-12th 1997, and buried structures, U.S. Pat. No. 5,543,637, have been employed to partially overcome these oxide limitations. In each of these arrangements, however, large electric fields are still present at the oxide interfaces thereby compromising the long-term oxide reliability. Finally, gate oxides are often fabricated on implanted semiconductor regions, which results in low oxide quality and reliability, particularly in power devices fabricated from SiC. An exemplary high-power thyristor device employing such a MOS gate structure can be found in the above article by A. K. Agarwal.
The need exists for monolithic, simply constructed, easily fabricated, power semiconductor devices in which the controlling gate structures are fabricated without oxides or dielectric insulators and are removed from the large electric fields within the device. Although non-oxide gate structures are preferred, the need also exists to provide a reliable, non-implanted semiconductor surface on which to fabricate gate oxides, for those power semiconductors which continue to employ MOS gates, and to isolate such gate oxide from the large electric field stresses.
SUMMARY OF THE INVENTION
A preferred embodiment according to the present invention provides for a semiconductor device comprising: (a) a semiconductor structure having top and bottom surfaces, the structure including a plurality of semiconductor layers defining a blocking p-n junction remote from both the surfaces, the structure including a control layer defining the top surface of the structure; a top conductive region extending from the top surface; a conductive tub region spaced apart from the top conductive region and extending from the top surface toward the blocking p-n junction at least through the control layer, the control layer including a field effect region disposed between the top conductive region and the conductive tub region; (b) a top ohmic contact in contact with the top surface at the top conductive region; (c) a bottom ohmic contact in contact with the semiconductor structure below the blocking p-n junction, the semiconductor layers being arranged so that when a potential is sustained between the top and bottom ohmic contacts, a major portion of the potential appears across the blocking p-n junction thereby forming depletion regions about the blocking p-n junction, and (d) a gate contact overlying the field effect region, whereby conductivity of the field effect region can be selectively controlled by a controlling potential on the gate contact to create and interrupt a conductive channel within the control layer, the top conductive region and the conductive tub region being coupled and decoupled by the conductive channel, the conductive tub region extending downwardly to the vicinity of the blocking p-n junction so that a least resistive current path including the top conductive region, the conductive channel and the conductive tub region is created between the top ohmic contact and the blocking p-n junction when the conductive channel is created.
In yet another embodiment, the semiconductor device further comprises a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the gate contact forming a Schottky contact such that the gate contact, the field effect region, the top conductive region and the conductive tub region constitute a MESFET. Alternatively, the semiconductor device may further comprise a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the field effect region having a gate conductive region extending from the top surface under the gate contact toward the control p-n junction such that the gate contact, the gate conductive region, the field effect region, the top conductive region and the conductive tub region constitute a JFET. Alternatively, the semiconductor device may further comprise a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the gate contact including an insulative layer on the top surface and a conductive contact on the insulative layer such that the gate contact, the field effect region, the top conductive region and the conductive tub region constitute a MOSFET. Yet another embodiment includes the semiconductor device in which the top conductive region includes a first subregion of same semiconductor type as the control layer and extending to a first depth from the top surface, a second subregion of opposite semiconductor type from the control layer extending to a second depth from the top surface and disposed between the first subregion and the field effect region, both of the subregions being in contact with the top ohmic contact, the gate contact including an insulative layer on the top surface and a conductive contact on the insulative layer such that the gate contact, the field effect region, the second subregion of the top conductive region and the conductive tub region constitute a MOSFET.
Additional embodiments of the invention include the semiconductor device in which the field effect region includes unimplanted epitaxially grown semiconductor defining the top surface in the field effect region, whereby the insulative layer includes an insulating compound on the unimplanted epitaxially grown semiconductor.
In one preferred embodiment, the semiconductor device may also be arranged such that the semiconductor device is a field controlled transistor, the conductive tub region extending at least to the blocking p-n junction and having a bottom end being disposed in the depletion region of the blocking p-n junction when the potential is sustained between the top and bottom ohmic contacts, the conductive tub region being alternatively depleted and undepleted of carriers in response to the selective controlling potential on the gate contact, whereby the transistor switches “off” and “on” respectively. In this embodiment the semiconductor device may have the top conductive region including a first subregion of same semiconductor type as the control layer and extending to a first d
Jackson, Jr. Jerome
Rutgers The State University
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