Multiplex communications – Communication techniques for information carried in plural... – Adaptive
Reexamination Certificate
1998-09-25
2003-07-15
Hsu, Alpus H. (Department: 2665)
Multiplex communications
Communication techniques for information carried in plural...
Adaptive
C370S503000, C370S537000
Reexamination Certificate
active
06594275
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to high speed data transmission and conversion systems. The present invention relates more particularly to a Fibre Channel host bus adapter having a multi-frequency clock buffer which facilitates conversion of asynchronous serial data into clock aligned, framed, parallel data in a manner which reduces power consumption by driving selected portions of a serial to parallel data converter at reduced clock speeds.
BACKGROUND OF THE INVENTION
High speed data transmission systems for communicating data between a computer and its associated peripherals, as well as between computers themselves, are well known. One example of such a high speed data communication system is Fibre Channel, which provides data transmission rates up to approximately 1 GHz when used with an optical fibre or coaxial cable transmission medium. When an optical fibre transmission medium is used, a Fibre Channel data transmission system can transmit data at such speeds even when the sender and receiver are separated by relatively great distances.
Data is transmitted over the optical fibre of a Fibre Channel system according to an asynchronous serial data transmission protocol. However, as those skilled in the art will appreciate, the internal architecture of contemporary computers is based upon parallel, byte-multiple signal buses (typically 8-bit, 16-bit or 32-bit buses). Thus, it is necessary to convert between the asynchronous serial data used for Fibre Channel communications and the parallel data used internally by the computer.
In a Fibre Channel system, byte-multiple parallel data must be converted by the transmitter into a 1 GHz asynchronous serial data signal for transmission along an optical fibre or coaxial cable and must be converted by the receiver from 1 GHz asynchronous serial data back into byte-multiple parallel data for internal use by a computer or peripheral.
In accordance with the Fibre Channel physical and signaling interface specification, defined in ANSI X3.230-1994, information to be transmitted over an optical fibre or wire cable is encoded, 8-bits at a time, into a 10-bit Transmission Character which is subsequently serially transmitted by bit. The data provided over a typical computer system parallel architecture is encoded and framed such that each data byte (8-bits from the point of view of the computer system) is formed into a Transmission Character in accordance with the Fibre Channel 8B/10B Transmission Code. The resulting 8B/10B Character is then transmitted as 10 sequential bits at approximately a 1 GHz data rate in accordance with the interface specification. Likewise, an incoming 8B/10B encoded Transmission Character must be serially received at an approximately 1 GHz data rate and converted (framed) into the corresponding 10-bit Transmission Character. The 10-bit Transmission Character is then further decoded into an 8-bit byte which is recognizable by such conventional computer architectures.
According to contemporary methodology, the conversion of high speed, e.g., 1 GHz, asynchronous serial data into byte-multiple data suitable for internal processing by a contemporary computer is performed by receiving the asynchronous serial data into a deserializer which comprises a serial in, parallel out shift register. The serial in, parallel out shift register is typically large enough-to capture an entire byte-multiple word of data, so as to facilitate the detection of a delimiter character, i.e., a character such as a comma which facilitates the proper framing of the data as byte-multiple parallel data words. The serial in, parallel out shift register must also be large enough to accommodate the byte-multiple data words themselves (which are typically of the same length as the delimiter character).
A pattern detection circuit facilitates identification and location of the delimiter character within the serial in, parallel out shift register and a word alignment circuit effects alignment of the framed delimiter and subsequent data words to a desired clock signal, e.g., a 100 MHz clock.
However, one problem commonly associated with such contemporary, high speed, serial to parallel data converters is the undesirably high power consumption associated therewith. A typical contemporary serial to parallel data converter suitable for converting approximately 1 GHz asynchronous serial data into 10-bit, 100 MHz parallel data comprises approximately 50 flip flops, of which approximately 40 are clocked at 1 GHz. Of course, each of these flip flops consumes electrical power and also contributes to the heat load of any integrated circuit of which it forms a part. Further, the clock driver required to drive the flip flops has to provide sufficient power to accommodate the fanout associated therewith.
The power consumption of such a contemporary, high speed, serial to parallel data converter is higher than desired because many of the flip flops thereof must be clocked at 1 GHz, thereby undesirably increasing power consumption, as discussed further below. One contemporary high speed serial to parallel data converter which utilizes fully synchronous design techniques is known to have a worst case power consumption of approximately 500 mW.
As those skilled in the art will appreciate, the heat dissipation of a circuit is directly proportional to the power consumed thereby. When a circuit is embodied in an integrated circuit chip, then it is particularly important to mitigate the heat dissipation thereof, so as to minimize the circuit's contribution to the total heat load of the integrated circuit chip. The total heat loading of an integrated circuit must be maintained below a predetermined level so that the heat can be extracted from the integrated circuit chip (such as by using a heat sink, fan, or thermoelectric cooler, if necessary). If the heat generated by an integrated circuit chip cannot be removed therefrom fast enough, then the temperature of the integrated circuit chip increases and the integrated circuit chip is subject to malfunction and/or premature failure. Since every individual circuit of an integrated chip contributes to the heat loading thereof, it is desirable to minimize the heat load contribution of each individual circuit, so as to reduce the heat loading of the entire integrated circuit chip.
It is well known that the power consumption of a circuit is directly proportional to the frequency at which the flip flops thereof operate, according to the formula: power=capacitance×frequency×voltage
2
. Thus, it is clear that reducing the frequency, i.e., clock rate, of selected flip flops by half reduces the power required to operate the selected flip flops by half as well.
In view of the foregoing, it is desirable to provide a serial to parallel data converter which operates with a substantial number of the flip flops thereof being clocked at a reduced rate, so as to mitigate power consumption and heat dissipation thereof.
SUMMARY OF THE INVENTION
The present invention specifically addresses and alleviates the above-mentioned deficiencies associated with the prior art by providing a serial to parallel data converter which has reduced power requirements. Reduced power consumption is facilitated by the use of an array of parallel registers for pattern detection which are clocked at a lower rate than the serial register of contemporary serial to parallel converters and therefore consume substantially less power than the contemporary serial register.
More particularly, the present invention comprises a Fibre Channel host bus adapter having a low power, high speed, serial to parallel data converter for converting asynchronous serial data into clock aligned, framed, parallel data. The data converter of the present invention comprises a serial in, parallel out register for receiving asynchronous serial data and for providing unframed parallel data. An array of parallel in, parallel out registers is configured to receive the unframed parallel data from the serial in, parallel out register and to move the re
Brady III W. James
Hsu Alpus H.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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