Fibonacci p-code parallel adder

Details Fibonacci p-code parallel adder Fibonacci p-code parallel adder

1979-05-14

1981-06-30

Malzahn, David H.

Boots, shoes, and leggings

G06F 749

Patent

active

042766087

ABSTRACT:
A Fibonacci p-code parallel adder comprises an augend register and an addend register having outputs coupled to the inputs of an end-of-addition detector and a monitoring unit and to the data inputs of a logic unit which comprises n rewrite AND gates. The AND gates have their inputs coupled to the complement and true outputs respectively of the augend and addend registers so as to provide for analyzing the condition of the flip-flips of the registers, and have their outputs coupled to the set inputs of the bit positions of the augend register and, via a delay unit, to the reset inputs of the bit position of the addend register, which provides for transfer of a 1 from the ith bit position of the addend register to the ith bit position of the augend register containing a 0. A Fibonnaci p-code minimizing unit has its inputs coupled to the outputs of the augend and addend registers, and has its outputs coupled to the normalize signal input of the augend register. This allows for the reduction of the codeword contained in the augend register to the minimal form with the codeword contained in the addend register being taken into consideration.

REFERENCES:
patent: 4159529 (1979-06-01), Stakhov

Affiliated with

Also associated with

Rating

Fibonacci p-code parallel adder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fibonacci p-code parallel adder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fibonacci p-code parallel adder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2434625