FFT address generation method and apparatus

Details FFT address generation method and apparatus FFT address generation method and apparatus

2005-06-14

2005-06-14

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06907439

ABSTRACT:
A method and apparatus are used to generate FFT data addresses based upon a computation stage value and a computation step value within that computation stage. The method includes the steps of generating a first data address by insertion at a bit insertion position a first bit between existing bits of a binary word and generating a second data address by inserting at the bit insertion position a second bit between existing bits of the binary word, wherein the binary word represents the computation step value. The apparatus includes a series of consecutive bit cells that generate the desired data addresses based upon a decoded value of the computation stage.

REFERENCES:
patent: 4393457 (1983-07-01), New
patent: 4689762 (1987-08-01), Thibodeau, Jr. et al.
patent: 5430667 (1995-07-01), Takano
patent: 5473556 (1995-12-01), Aguilar et al.
patent: 5491652 (1996-02-01), Luo et al.
patent: 5991788 (1999-11-01), Mintzer
patent: 6035313 (2000-03-01), Marchant

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