Fishing – trapping – and vermin destroying
Patent
1989-10-17
1992-10-06
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 41, 437200, H01L 2124, H01L 21265, H01L 21336
Patent
active
051531453
ABSTRACT:
A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adajcent double or triple-layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.
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patent: 4727038 (1988-02-01), Watabe et al.
patent: 4818714 (1989-04-01), Haskell
patent: 4843023 (1989-06-01), Chiu et al.
Tsang et al., "Fabrication of High Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEEE Journal of Solid State Circuits, vol. SC-17, No. 2, Apr. 1982, pp. 220-226.
IEEE Electron Device Letters V. 9(4), (1988), "LDD MOSFET's Using Disposable Side Wall Spacer Technology," J. R. Pfiester, pp. 189-192.
VLSI Technology Symposium (1988), "Simultaneous Formation of Shallow-Deep Stepped Source/Drain for Submicron CMOS," C. W. Oh et al., pp. 73-74.
Lee Kuo-Hua
Lu Chih-Yuan
Sung Janmye
AT&T Bell Laboratories
Chaudhuri Olik
Rehberg John T.
Wilczewski M.
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