FET with gate spacer

Details FET with gate spacer FET with gate spacer

1992-04-03

1997-10-21

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 40SW, 437 41RLD, 437 41GS, 437 41SW, 437 30, 437 44, H01L 21336, H01L 2128

Patent

active

056795890

ABSTRACT:
A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.

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Tsang et al., "Fabrication of High Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEEE Journal of Solid State Circuits, vol. SC-17, No. 2, Apr. 1982, pp. 220-226.
European Search Report, dated Nov. 10, 1991.

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