FET with Fermi level pinning between channel and heavily doped s

Details FET with Fermi level pinning between channel and heavily doped s FET with Fermi level pinning between channel and heavily doped s

1985-05-08

1987-10-06

Larkins, William D.

Metal treatment

Stock

Ferrous

357 4, 357 22, 357 232, 148DIG53, 148DIG72, 148DIG88, 148DIG97, H01L 29205, H01L 2980

Patent

active

046986529

ABSTRACT:
Herein disclosed is a semiconductor device in which control means for carriers migrating in a first semiconductor includes an interface state layer lying on the first semiconductor and a second conductor layer lying on the interface state layer. The interface state layer has its Fermi level pinned to that of the second semiconductor layer. By thus constructing an FET or the semiconductor device, an inversion or accumulation layer can be easily formed in the interface merely by applying a voltage to the control means.

REFERENCES:
patent: 4424525 (1984-01-01), Mimura
patent: 4532533 (1985-07-01), Jackson
patent: 4559547 (1985-12-01), Shiraki
Electronics Letters, vol. 18, No. 4, Feb. 18, 1982, pp. 180-181.
J. Appl. Phys., vol. 54, No. 5, May 1983, pp. 2795-2806.
Thin Solid Films, vol. 130, No. 112, May 1983, pp. 155-166.
Japan J. Appl. Phys., supp. 22-1, 1983, pp. 11-19.
International J. of Electronics, vol. 52, No. 1, Jan. 1982, pp. 13-22.
Electronics Letters, vol. 14, No. 16, Aug. 3, 1978, pp. 500-502.

Affiliated with

Also associated with

Rating

FET with Fermi level pinning between channel and heavily doped s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FET with Fermi level pinning between channel and heavily doped s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FET with Fermi level pinning between channel and heavily doped s will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2120779