Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2001-07-31
2003-01-07
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S280000, C257S282000, C257S284000, C257S368000, C257S213000, C257S471000
Reexamination Certificate
active
06504190
ABSTRACT:
This application is based on Japanese Patent Application 2000-299577, filed on Sep. 29, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a field effect type semiconductor device having a Schottky gate electrode and being excellent in high frequency characteristics and to its manufacture method.
b) Description of the Related Art
FIG. 4A
shows an example of a field effect transistor which is suitable for amplification in the high frequency bandwidth. On the surface of a semi-insulating GaAs substrate
100
, a channel layer
101
is formed which is made of Si doped n-type GaAs. On this channel layer
101
, a cap layer
102
is formed which is made of undoped GaAs. An opening
102
a
for a gate electrode is formed through the cap layer
102
.
A gate electrode
105
is formed on the channel layer
101
exposed on the bottom of the opening
102
a.
The gate electrode
105
is in Schottky contact with the channel layer
101
. A drain electrode
106
is formed on the cap layer
102
on one side of the gate electrode
105
, whereas a source electrode
107
is formed on the cap layer
102
on the other side. The drain electrode
106
and source electrode
107
are in ohmic contact with the channel layer
101
via the cap layer
102
. The source electrode
107
passes over the gate electrode
105
and extends near to the drain electrode
106
.
FIG. 4B
is a plan view of the field effect transistor shown in
FIG. 4A. A
cross sectional view taken along one-dot chain line A
4
—A
4
shown in
FIG. 4B
corresponds to FIG.
4
A. Two gate electrodes
105
are disposed in parallel. The source electrode
107
is disposed in an area between the two gate electrodes
105
, and the both end portions thereof overlap the gate electrodes
105
. The drain electrodes
106
are disposed outside of the two gate electrodes
105
.
A portion of the source electrode
107
passing over the gate electrode
105
electrically shields the gate electrode
105
from the drain electrode
106
. It is therefore possible to reduce a parasitic capacitance Cgd between the gate electrode and the drain electrode.
In the semiconductor device shown in
FIGS. 4A and 4B
, since the source electrode
107
covers the gate electrode
105
, the parasitic capacitance Cgs between the gate electrode and source electrode increases. Therefore, the effect of improving the high frequency characteristics by reducing the parasitic capacitance Cgd between the gate electrode and drain electrode is lowered or may be cancelled out.
As shown in
FIG. 4C
, if the portion of the source electrode
107
covering the gate electrode
105
is made to have a comb tooth shape, the parasitic capacitance Cgs between the gate electrode and source electrode can be prevented from being increased. However, the shielding effect of the source electrode of the comb tooth shape is not sufficient because it has areas without a comb tooth. For example, the effect to shield the lines of electric force from the gate electrode
105
to the drain electrode
106
is small in the area without a comb tooth. The shielding effect becomes small particularly if the pitch between comb teeth is larger than ¼ of the wavelength of electromagnetic waves corresponding to the operation frequency.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device and its manufacture method, capable of sufficiently shielding the gate electrode from the drain electrode while suppressing an increase of the parasitic capacitance between the source electrode and gate electrode.
According to one aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; a gate electrode in Schottky contact with a surface of the semiconductor substrate, the gate electrode extending in a first direction; a drain electrode disposed on one side of the gate electrode, spaced apart from the gate electrode by some distance, and in ohmic contact with the semiconductor substrate; and a source electrode formed on the surface of the semiconductor device, the source electrode including a main part in ohmic contact with the semiconductor substrate in a region across the gate electrode from the drain electrode, a shielding part disposed between the gate and drain electrodes as viewed along a direction normal to the surface of the semiconductor substrate, the shielding part extending in the first direction, and an overhanging part passing over the gate electrode and connecting the shielding part with the main part, the size of the overhanging part along the first direction is smaller than the side of the shielding part.
The shielding part electrically shields the gate electrode from the drain electrode. The size of the overhanging part in the first direction is smaller than that of the shielding part. It is therefore possible to decrease the overlapped area between the gate and source electrodes and reduce the parasitic capacitance therebetween.
According to another aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; a gate electrode in Schottky contact with a surface of the semiconductor substrate, the gate electrode extending in a first direction; a drain electrode disposed on one side of the gate electrode, spaced apart from the gate electrode by some distance, and in ohmic contact with the semiconductor substrate; and a source electrode formed on the surface of the semiconductor device, the source electrode being in ohmic contact with the semiconductor substrate in a region across the gate electrode from the drain electrode, passing over the gate electrode, and extending to a space between the drain and gate electrodes, the source electrode having an opening partially overlapping the gate electrode as viewed along a direction normal to the surface of the semiconductor substrate.
Since the source electrode extends to a space between the drain and gate electrodes, the gate electrode can be electrically shielded from the drain electrode. Since the opening partially overlapping the gate electrode is formed through the source electrode, the overlapped area between the source and drain electrodes can be decreased and the parasitic capacitance therebetween can be reduced.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming, on a surface of a semiconductor substrate, a gate electrode being in Schottky contact with the semiconductor substrate and extending in a first direction and first and second ohmic contact electrodes on both sides of the gate electrode disposed spaced apart from the gate electrode by some distance; covering the gate electrode and the surface of the semiconductor substrate on both sides of the gate electrode with a first resist pattern; forming a conductive groundwork layer on the resist pattern and the first and second ohmic electrodes; forming second and third resist patterns on the ground work layer, the second resist pattern being disposed at a position nearer to the first ohmic electrode than the gate electrode and extending in the first direction, the second resist pattern being disposed partially overlapping the first resist pattern as viewed along a direction normal to the substrate surface, the third resist pattern being disposed at position nearer to the second ohmic electrode than the second resist pattern and partially overlapping the gate electrode; plating conductive material on the groundwork layer by using the second and third resist patterns as a mask; removing the second and third resist patterns; removing the groundwork layer exposed on a bottom of an opening formed after the second and third resist patterns are removed; and removing the first resist pattern.
The plated layer on the first ohmic electrode functions as a drain electrode, and the plat
Fujitsu Quantum Devices Limited
Greene Pershelle
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