Fet-teld combination with capacitively coupled output electrode

Details Fet-teld combination with capacitively coupled output electrode Fet-teld combination with capacitively coupled output electrode

1977-07-18

1979-03-20

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307214, H01L 2726, H03K 1940, H03K 1908

Patent

active

041456246

ABSTRACT:
A field effect transistor (FET) is connected in series to a transferred electron logic device (TELD), the TELD being a non-linear load resistor for the FET. The current thresholding property of the TELD and the saturation characteristics of the FET are utilized to produce an output pulsed signal of substantial voltage gain with fast rise time and short pulse width. An output electrode is capacitively coupled to the TELD to provide an output pulsed signal of alternating polarity for direct interconnection of devices in cascaded circuits.

REFERENCES:
patent: 3115584 (1963-12-01), Yao
patent: 3848141 (1974-11-01), Sterzer
patent: 3980896 (1976-09-01), Kato
patent: 4000415 (1976-12-01), Curtice
IEEE Journal of Solid State Electronics, vol. SC-7, No. 3, Jun. 1972, pp. 231-237, "A Most Inverter with Improved Switching Speed", by J. Kooman & Akker.
IEEE Journal of Solid State Circuits - "Gunn Device Gigabit Rate Digital Microcircuits" by K. Mause, A. Schlachetzki, E. Hesse and H. Salow; pp. 2-11, Feb. 1975.
Electronic Letters, "Integration of GaAs MESFETS and Gunn Elements in a 4-Bit Gate Device" by N. Hashizume and S. Kataoka; pp. 370-372, Jul. 1976, vol. 12, No. 15.

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