Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific voltage responsive fault sensor
Reexamination Certificate
2000-11-15
2003-03-25
Sircus, Brian (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific voltage responsive fault sensor
C361S056000
Reexamination Certificate
active
06538867
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic switches. In particular, the present invention relates to semiconductor switches, including those formed of one or more metal-oxide-semiconductor (MOS) transistors. More particularly, the present invention relates to P-type MOS (PMOS) field effect transistor (FET) bus switches.
2. Description of the Prior Art
Developments in semiconductor technology have created the capability to produce low-cost, highly reliable switches that are, effectively, implementations of mechanical relays. They have been found to be of particular use, when implemented, as single pole, single throw, type relays, but are not limited thereto. Semiconductor switches are being used more and more as replacements for the prior mechanical relays, due to the high switching speed available as well as their ability to transfer relatively high currents without failure. These switches are often referred to as transfer gates or pass transistors as they employ the characteristics of transistors—usually MOS transistors—to either permit or prevent the passage of a signal.
It is well known that switches are widely used in many fields. They are used in all variety of large- and small-scale consumer products, including, but not limited to, automobiles and home electronics. They can be and are used as analog routers, gates, and relays. They are used as digital multiplexers, routers, and gates as well.
A number of prior-art transfer gates have been developed for digital and analog applications. Recent innovations have provided methods for operation at lower power supply potentials such as 3.3 Volts and 2.5 Volts, while providing some method of maintaining isolation when input values go beyond high- and low-potential power rail values. That is, when a transfer gate input potential exceeds the high-potential rail Vcc positively, or it exceeds the low-potential rail GND negatively. One such device that has been in relatively common use is shown in FIG.
1
.
A complementary pair of transistors, NMOS transistor M
1
and PMOS transistor M
2
conduct signals between nodes A and B, where each of those nodes is couplable to an extended circuit. When a control signal OEN (shown in
FIG. 1
associated with node A as the input for purposes of illustration only, but which can also be associated with node B as the input) is a logic “high” or “1,” transistor M
1
is turned on, and as a result of the inversion produced by inverter I
1
, transistor M
2
is also on. In this condition, the two transistors are “on” and the potential at node B is essentially the same as the potential at node A. When OEN is at a logic “low” or “0,” both transistors are off and there exists a high impedance for the transfer of any signal between nodes A and B. This is true for all potentials at node A or B that are less than the potential of high-potential power rail Vcc and greater than low-potential power rail GND. However, when either the input or the output node is greater than Vcc or less than GND, the potential associated with the typical logic low at the gate of transistor M
1
and a typical logic high at the gate of M
2
is insufficient to keep those transistors off. For a potential greater than Vcc, M
2
will turn on, for a potential less than GND, M
1
will turn on, irrespective of the logic level applied at input OEN. As a result, an overvoltage condition at either the input or the output will cause M
1
and M
2
to permit a signal to pass through that the OEN deems should be blocked. An undervoltage condition will likewise be passed under the same OEN condition.
For the purpose of this disclosure, the term “overvoltage” means the potential variation noted that occurs under static (DC) conditions as well as dynamic (AC) conditions. For that reason, overvoltage may be used interchangeably with overshoot. Passage of an overvoltage between nodes A and B when the signal at OEN requires the switch to be off is undesirable in that it will cause the passage of electric signals between the two nodes when none should be passed. This can disrupt the bus.
A device designed to resolve at least one portion of the problems associated with the complementary transfer gate of
FIG. 1
is shown in FIG.
2
. The device involves removal of NMOS transistor M
1
, leaving PMOS transistor M
2
coupled between nodes A and B, where node A is the input from, or output to, a first extended circuit, and node B is the input from, or output to, a second extended circuit. As before, control node OEN is designed to control enablement of M
2
. In operation, a logic level HIGH from OEN through inverter IV
1
to the gate of M
2
turns M
2
on and thereby permits a signal to pass between nodes A and B. A logic level LOW turns M
2
off and blocks the transfer of the signal between A and B. Elimination of transistor M
1
resolves the problem when the potential at node A or node B exceeds GND because that transistor is not there to be turned on. Unfortunately, that does not eliminate the possibility that the transfer gate will turn on when it should be off under conditions of positive voltage exceeding Vcc.
It would be desirable to have a transfer gate operating with a single PMOS transistor as the FET switch substantially as shown in the circuit of FIG.
2
. Such a switch would have reasonable resistance and capacitance characteristics when compared to alternative solutions requiring additional switching components. However, the prior single PMOS switch of
FIG. 2
is unacceptable during overvoltage conditions in that there is a parasitic diode connected between either the source or drain of the transistor and its bulk. As can be seen, the bulk of the transistor is tied to the high-potential power rail Vcc. During overvoltage conditions at the high-potential rail, the parasitic diode conducts current from Vcc to either the input node or the output node, depending upon which is at a potential that is higher than the potential of Vcc. Under that condition, current will move from the output node to the input node, thereby causing a disruption of signal transmission otherwise occurring at the output node. This can occur independent of the condition of the enable signal at OEN. Such a concern is of increasing importance as circuits having mixed power supplies are coupled together and the possibility of overvoltage becomes increasingly likely.
Two characteristics of the physical structure of the single PMOS FET switch cause this clearly undesirable parasitic conduction condition. The first is the formation of a parasitic bipolar PNP transistor. The second is the unintended turning on of the PMOS FET switch in certain overvoltage situations. With regard to the first condition, the drain (P-type collector), transistor bulk (N-type base), and source (P-type emitter) form the PNP transistor. Transistor fabrication steps currently in use in sub-micron processes can yield in this common-base parasitic bipolar transistor a current gain that is the equivalent of a common-emitter gain (&bgr;) of about 10. Thus, during an overvoltage condition, the relatively small current moving from the high-potential rail to the more positive input node yields a ten-fold increase in the undesired parasitic current moving from the output node to the input node. Of course, in an ideal FET switch there should be no current flowing from the output node to the input node unless specifically enabled.
The other undesirable condition associated with the parasitic diode of the prior single-FET switch relates to the undesired conduction by the FET switch during an overvoltage event. Specifically, if current is developed from the high-potential rail through a lower-potential circuit node there is a potential drop across the substrate/bulk resistance that will cause the transistor to conduct current from one circuit node to the other, even during sub-threshold conditions. That conduction is significant enough to cause leakage resulting in unintended signal switching in certain instances.
It may be seen that it is necessary to isolate
Goodell Trenor F.
Richards Jennifer
Cesari and McKenna LLP
Fairchild Semiconductor Corporation
Kitov Z
Paul, Esq. Edwin H.
Sircus Brian
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