FET structure arrangement having low on resistance

Details FET structure arrangement having low on resistance FET structure arrangement having low on resistance

1987-03-18

1988-10-04

Edlow, Martin H.

357 238, 357 231, 357 41, H01L 2978, H01L 2702

Patent

active

047758791

ABSTRACT:
A vertical field effect transistor is provided which has its sources arranged in a pattern to essentially eliminate inactive common drain area between the sources. The preferred arrangement is to use rectangular source areas to form columns and rows in the arrangement. Every other row is shifted so that a source in a shifted row is positioned between sources in an adjacent row. The rows are then spaced closer together thereby achieving the substantial elimination of inactive drain area. The elimination of inactive drain area results in low on resistance during the conductive state of the vertical field effect transistor.

REFERENCES:
patent: 4152714 (1979-05-01), Hendrickson et al.
patent: 4532534 (1985-07-01), Ford et al.
patent: 4586072 (1986-04-01), Nakatani et al.
patent: 4630084 (1986-12-01), Tihanyi
patent: 4672407 (1987-06-01), Nakagawa et al.
Power Integrated Circuits, McGraw-Hill, Inc., 1986, by Paolo Antognetti, pp. 3.34-3.42.
Electronic Engineering, Feb. 1983, "Siliconix Undercuts Power Mosfet Industry", p. 15.

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