FET reference voltage generator which is impervious to input vol

Details FET reference voltage generator which is impervious to input vol FET reference voltage generator which is impervious to input vol

1987-02-09

1989-03-21

Beha, Jr., William H.

Electricity: power supply or regulation systems

In shunt with source or load

Using diode

307304, 323312, 323313, G05F 324

Patent

active

048146862

ABSTRACT:
A reference d.c. voltage generator is disclosed which includes a series circuit for first and second field effect transistors or FETs. The first FET serves as a high-impedance constant current supply, while the second FET functions as a resistor for generating at its soure a reference d.c. voltage. A series circuit of two FETs is connected between the gate and source of the first FET to bias the first FET such that a current flowing therein is kept constant, whereby the gate-source voltage thereof can be stabilized even when the power supply voltage is fluctuated.

REFERENCES:
patent: 3806742 (1974-04-01), Powell
patent: 3823332 (1974-07-01), Feryszka et al.
patent: 4454467 (1984-06-01), Sakaguchi
patent: 4641081 (1987-02-01), Sato et al.
K. Itoh et al. "An Experimental 1 Mb DRAM with On-Chip Voltage Limiter" ISSCC Dig. Tech. Paper p. 282 (1984).
T. Mano et al. "Circuit Techniques for a VLSI Memory." IEEE J. Solid-State Circuits vol. SC-18, p 463 (1983).

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