FET Negative resistance circuits

Details FET Negative resistance circuits FET Negative resistance circuits

1982-05-20

1985-01-01

Grimm, Siegfried H.

Oscillators

Solid state active element oscillator

Transistors

331115, 333217, H03K 3354, H03H 1100

Patent

active

044918070

ABSTRACT:
FET circuitry is described which may be substituted for a programmable unijunction transistor particularly on CMOS-FET integrated circuits. The FET circuitry is arranged between first and second terminals defining a conduction path exhibiting a negative resistance characteristic and a control terminal for establishing the peak voltage of such characteristic. A P-type MOS transistor has its source and gate electrodes respectively connected to the first and control terminals. A current mirror amplifier comprising N-type MOS transistors has its input terminal connected to the drain electrode of the P-type transistor, its output terminal connected to the control terminal and its common terminal connected to the second terminal of the circuitry.

REFERENCES:
patent: 3843933 (1974-10-01), Ahmed
patent: 3863169 (1975-01-01), Knight
patent: 3887884 (1975-06-01), Suzuki
patent: 4230999 (1980-10-01), Ahmed
The Synthesis of Integrable, Nearly Sinusoidal Potentially Bistable Oscillators, IEEE JSSC vol. scl, No. 2, Dec. 1966, pp. 111-117.
J. D. Lenk, Handbook for Transistors, Prentice Hall, Inc., Englewood Cliffs, N.J., 1976, pp. 178-185.

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