FET having minimized parasitic gate capacitance

Details FET having minimized parasitic gate capacitance FET having minimized parasitic gate capacitance

1994-01-03

1995-10-24

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

257289, 257195, H01L 2920, H01L 2922

Patent

active

054612446

ABSTRACT:
A HIGFET having a gate pad situated over a non conducting portion of the channel layer of the heterostructure wafer. The method of producing this device involves application of a very thin layer of gate metal on the wafer to protect the wafer surface during further processing. A photoresist coating is formed over the active area of the channel layer of the FET. An ion isolation implantation is applied to the wafer resulting in a non conducting portion of the channel layer that is not covered by the photoresist layer. The photoresist layer is removed and a thick layer of gate metal is applied on the thin layer of gate metal. The gate layers are fashioned into a pad over the non conducting portion of the channel layer and at least one finger over the conducting portion of the channel layer, resulting in the gate having minimized parasitic gate capacitance.

REFERENCES:
patent: 4805005 (1989-02-01), Usagawa et al.

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