FET gate current limiter circuits

Details FET gate current limiter circuits FET gate current limiter circuits

1986-03-24

1987-10-20

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307544, 307559, 307568, H03K 1710, H03K 17284, H03K 19003, H03K 19094

Patent

active

047016434

ABSTRACT:
A GaAs logic circuit uses a first FET to control the application of a logic signal from an input to an output. The first FET inherently has parasitic gate-to-source and gate-to-drain diodes. A control signal applied to the gate of the first FET controls the application of the logic signal to the output through the first FET. For a first FET that is an enhancement mode GaAs device, the gate current tends to forward bias such diodes under all operating conditions and tends to significantly increase the gate current. For a first FET that is a depletion-mode device, adverse operating temperatures can cause such tendency to forward bias these diodes and other circuit diodes. A limiter FET connected to the gate to limit the gate current and thus limits the forward biasing of the parasitic and circuit diodes. This reduces the effect on the gate current of variations in the power supplies to the FET, process variations and operating temperature variations. Limiting the gate current also limits the voltage drop resulting from the source resistance of the first FET, maintaining the voltage swing of the logic signal at the output at desired levels. If the gate current were not limited, the resulting greater forward bias of those diodes would cause an increase in the current drain from a voltage supply that biases the first FET. The unlimited forward bias would also result in a greater voltage drop from drain-to-source across the first FET, reducing the V.sub.OL at the output and resulting in lower noise margin.

REFERENCES:
patent: 4300064 (1981-11-01), Eden
patent: 4393315 (1983-07-01), Stickel et al.
patent: 4405870 (1983-09-01), Eden
patent: 4418292 (1983-11-01), Cserhalmi et al.
patent: 4471238 (1984-09-01), Hickling
patent: 4488064 (1984-12-01), Vance
Nuzillat et al, "Low Pinch-Off Voltage FET Logic (LPFL): L.S.I. Oriented Logic Approach Using Quasinormally Off GaAs MESFETs"; IEE Proc., vol. 127, Pt. I, No. 5, pp. 287-296.
Hartgring, C. D. et al., "Silicon MESFET Digital Circuit Techniques", IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, (10-81), pp. 578-584.
Lehovec, K., et al., "Analysis of GaAs FET's for Integrated Logic", IEEE Transactions on Electron Devices, vol. ED-27, No. 6 (6-80), pp. 1074-1091.

Affiliated with

Also associated with

Rating

FET gate current limiter circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FET gate current limiter circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FET gate current limiter circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1614174