FET for high reverse bias voltage and geometrical design for low

Details FET for high reverse bias voltage and geometrical design for low FET for high reverse bias voltage and geometrical design for low

1986-08-08

1988-04-05

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 45, 437 49, 437913, H01L 21425, H01L 2972

Patent

active

047359145

ABSTRACT:
Field-effect transistor devices are provided having a relatively substantial capability to withstand reverse bias voltages. This capability is provided through providing shields in these devices near junctions in such devices which are subject to breakdown under large reverse bias voltages, these shields being operable at selected voltages. The device can also be provided having a relatively low "on" condition resistance between the source and drain terminals thereof by virtue of a geometrical design choice. A method for fabricating one such device is also disclosed.

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Dill, "A New Insulated Gate Tetrode with High Drain Breakdown Potential and Low Miller Feedback Capacitance", IEEE Trans. on Electron. Devices, vol. ED-15, No. 19--Oct. 68, pp. 717-726.

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