FET differential amplifier

Amplifiers – With semiconductor amplifying device – Including differential amplifier

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330257, 330277, 307356, H03F 345

Patent

active

047163801

ABSTRACT:
A differential amplifier (10) has two input terminals (16,18), an output terminal (20) together with power terminals (12,14). The differential amplifier comprises two or more stages with each stage having a pull-up transistor (22) and a pull-down transistor (26). The first input terminal (16) is connected to alternate stages of the amplifier (10) and the second input terminal (18) is connected to the remaining alternate stages of the amplifier (10). The gain of the various stages is determined by fabrication of the transistors, in particular, the geometries of the transistor channels. A state transition at an output terminal (20) is produced when the voltages at the input terminals (16,18) are approximately equal and the gains of the various stages are essentially equal. A state change at the output terminal (20) is caused to occur when there is a given voltage offset between the voltages at the input terminal (16,18) when the gains of the two sets of alternate stages of the amplifier (10) are made unequal.

REFERENCES:
patent: 3967208 (1976-06-01), Baylac et al.
patent: 4240039 (1980-12-01), Mihalich
patent: 4243945 (1981-01-01), Eckert
patent: 4247824 (1981-01-01), Hilbourne
Tsivids et al, "An Integrated NMOS Operational Amplifier with Internal Compensation", IEEE Journal of Solid-State Circuits, vol. SC-11, No. 6, Dec. 1976, pp. 748-753.

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