FET device with reduced gate overlap capacitance of source/drain

Details FET device with reduced gate overlap capacitance of source/drain FET device with reduced gate overlap capacitance of source/drain

1977-02-17

1977-11-01

James, Andrew J.

357 54, 357 59, H01L 2978, H01L 2934, H01L 2904

Patent

active

040568253

ABSTRACT:
A metal gate transistor is fabricated to have reduced gate overlap of source/drain regions and increased oxide thickness over the diffused regions whereby parasitic capacitance is reduced and switching speed is increased. The method comprises the steps of (1) selecting an appropriate insulating thickness over a semiconductor substrate, (2) forming source/drain diffused regions in the substrate through openings in the insulating layer at appropriate diffusion temperatures, (3) selecting an appropriate drivein and regrowth temperature whereby the insulating layer thickness over the diffused region is greater than that over the non-diffused region and out diffusion of the diffused regions is minimized, (4) etching the region between the source/drain to form a gate area and (5) growing a prescribed gate insulation thickness for a metal gate whereby the gate insulation overlap of the diffused region and the thickness of the gate insulation overlap of the diffused region reduce the parasitic capacitance and increase the switching speed of the resulting metal gate transistor relative to prior art transistors.

REFERENCES:
patent: 3787251 (1974-01-01), Brand et al.
patent: 3793090 (1974-02-01), Barile et al.
patent: 3863330 (1975-02-01), Kraybill et al.
patent: 3899372 (1975-08-01), Esch
patent: 3909306 (1975-09-01), Sakamoto et al.
patent: 3913211 (1975-10-01), Seed et al.
patent: 3936859 (1976-02-01), Dingwall
patent: 3958323 (1976-05-01), DeLaMoneda
patent: 4015281 (1977-03-01), Nagata et al.
patent: 4016587 (1977-04-01), DeLaMoneda

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