FET Containing stacked gates

Details FET Containing stacked gates FET Containing stacked gates

1979-10-19

1981-08-04

Edlow, Martin H.

357 59, H01L 2978

Patent

active

042825407

ABSTRACT:
A field effect transistor (FET) comprising a floating gate and a control gate in a stacked relationship with each other and being self-aligned with each other and self-aligned with respect to source and drain regions. The fabrication technique employed comprises delineating both the floating gate and control gate in the same lithographic masking step.

REFERENCES:
patent: 3825945 (1974-07-01), Masuoka
patent: 3836992 (1974-09-01), Abbas
patent: 3868187 (1975-02-01), Masuoka
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patent: 3984822 (1976-10-01), Simko
patent: 3996657 (1976-12-01), Simko
patent: 4004159 (1977-01-01), Rai
patent: 4099196 (1978-07-01), Simko
patent: 4115795 (1978-09-01), Masuoka
patent: 4142926 (1979-03-01), Morgan
patent: 4209849 (1980-07-01), Schrenk

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