Amplifiers – With semiconductor amplifying device – Including current mirror amplifier
Reexamination Certificate
2002-02-20
2003-01-14
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including current mirror amplifier
C330S285000, C330S296000, C330S297000
Reexamination Certificate
active
06507246
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of transconductance amplifiers, and particularly to methods of controlling the transconductance of MOS transistors.
2. Description of the Related Art
A useful element of electronic circuit design is the transconductance amplifier; i.e., a voltage-to-current amplifier having an associated transconductance g
m
(gain) which is expressed in units of A/V. Such amplifiers are constructed from transistors, which exhibit transconductance. However, the transconductance of a transistor is influenced by several factors which can adversely affect amplifier performance. For example, the transconductance of a MOS transistor depends on a number of factors, including transistor size, operating current, and temperature. These last two dependencies are subject to broad variations due to manufacturing tolerances, making it difficult to accurately set the transconductance and maintain it against temperature variation.
One approach to minimizing transconductance variation is described in “Understanding Wide-Band MOS Transistors”, J. Steininger, IEEE Circuits and Devices, Vol. 6, No. 3, pp. 26-31 (May 1990). Steininger proposes a circuit which is a MOS version of a self-biasing Widlar current source, comprising two PMOS and two NMOS transistors (two of which are diode-connected) and a resistor R
b
. When the transistors are properly sized, the transconductance becomes directly proportional to the resistance of R
b
.
However, this circuit suffers from a couple of weaknesses. First, two of the circuit's transistors operate at zero gate-drain potential, while the other two do not. This subjects the second two transistors to the channel length modulation effect. Since these transistors experience the effects of variations in the supply voltage, their characteristics may be different than those of the first two transistors, and a biasing error may result.
A second problem is that the circuit has a second equilibrium state, when all currents are zero. Overcoming this “start-up” problem requires a start-up circuit, which typically introduces a small current into one of the diode-connected transistors. Unfortunately, this current inevitably corrupts the circuit by ensuring that one of the diode currents is larger than the other, which worsens the impact of the channel length modulation effect problem discussed above.
Another approach is described in Johns and Martin, “Analog Integrated Circuit Design”, pp. 248-251 (1997). Here, a bias circuit is made from two PMOS and four NMOS transistors and a resistor. A cascading arrangement reduces the aforementioned channel length modulation effect somewhat, but not completely. In addition, the starting problem mentioned above also afflicts this circuit.
SUMMARY OF THE INVENTION
A FET circuit is presented which overcomes the problems noted above. The four-transistor circuit sets the transconductance of a FET using a resistor. The channel length modulation effect is practically eliminated, there is no starting problem, and all transistors are of like polarity.
The circuit comprises a resistor R
1
and first and second FETs series-connected in sequence between a supply voltage and a circuit common point, and third and fourth FETs and a bias current source series-connected in sequence between the supply voltage and the circuit common point. The drain and gate of the fourth FET are connected to the gate of the second FET and the gates of the first and third FETs are cross-coupled to the drains of the third and first FETs, respectively. The bias current source provides a starting current for the circuit. All FETs are of like polarity.
When the circuit is arranged as described, and the threshold voltages of the first and second FETs are matched, the transconductance of the second FET is directly proportional to 1/R
1
. Since resistors can be made much more predictably than transistors, the invention makes the transconductance of the second FET much more robust against temperature change and manufacturing variability than it might be otherwise. The current and/or operating voltages of the FET can in turn be used to bias other FETs in a very reproducible way to fix the transconductance of an amplifier according to the selected resistor value.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.
REFERENCES:
patent: 4389619 (1983-06-01), Limberg
patent: 5986507 (1999-11-01), Itakura et al.
patent: 2002/0027476 (2002-03-01), Soldavini
patent: 633661 (1982-12-01), None
Kimura “Low Voltage Techniques for Bias Circuits” IEEE Transactions on Circuits and Systems I vol. 44 Issue 5, May 1997.*
Understanding Wide-Band MOS Transistors, Circuits and Devices, John M. Steininger, p. 26-31, date unknown.
Analog Integrated Circuit Design, Chapter 5, Basic Opamp Design and Compensation, David Johns, Ken Martin, p. 248-251 (1997) May 1997.
Analog Devices Inc.
Koppel, Jacobs Patrick & Heybl
Shingleton Michael B
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