FET Circuit for converting TTL to FET logic levels

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307264, H03K 19092, H03K 19094

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active

044069561

ABSTRACT:
This invention relates to a field effect transistor level converter for converting bipolar transistor logic levels to field effect transistor logic levels. First and second field effect transistors have their source and gate electrodes connected in common. The bipolar input signal is received at the common source connection while the gate electrodes receive a fixed reference potential that is equal to the threshold voltage VT plus the lowest possible high binary level of the bipolar input logic. The drain electrode of the first field effect transistor is connected to the output terminal of the level converter and the source electrode of a source follower transistor. The drain electrode of the second transistor is connected to a load device and to the gate of the source follower transistor which has its drain electrode connected to VH. This arrangement produces at the first output terminal a potential swing of approximately 0 to 7 volts in response to an input signal in the range of 0.8 to 2.0 volts.

REFERENCES:
patent: 3708689 (1973-01-01), Lattin
patent: 3710271 (1973-01-01), Putnam
patent: 3906254 (1975-09-01), Lane et al.
patent: 4023050 (1977-05-01), Fox et al.
patent: 4129794 (1978-12-01), Dickson et al.
patent: 4258272 (1981-03-01), Huang
patent: 4307308 (1981-12-01), Sano
IEEE Jrnl. of Solid State Circuits, vol. SC-13, No. 3, Jun. 1978; pp. 333-338, E. Arai et al.

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