FET bias circuit

Details FET bias circuit FET bias circuit

2008-09-02

2008-09-02

Nguyen, Patricia (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including particular biasing arrangement

C330S277000, C330S311000

Reexamination Certificate

active

11568457

ABSTRACT:
The present invention discloses an FET (Field Effect Transistor) bias circuit comprising a current-changing information circuit having a power source, a resistor connected to the signal output end of this circuit, the other end of the resistor connected to a reference voltage source, and the node between the resistor and the current-changing information circuit acting as the output end providing voltage-changing information; and a voltage divider circuit connected to at least one voltage source, and connected to the output end providing the voltage-changing information; the current in a signal FET is controlled by providing the voltage-changing information at the output end to the voltage divider circuit, and getting a dividing voltage from the voltage divider circuit as an output end of the FET bias circuit. The bias circuit of the present invention causes the static drain current of the signal FET to remain constant, and reduces the variation of the static drain current of the signal FET of each chip made from an entire wafer. Its cost is low, its size is small, and it is easy to be integrated and fabricated.

REFERENCES:
patent: 5757237 (1998-05-01), Staudinger et al.
patent: 6046642 (2000-04-01), Brayton et al.
patent: 6201444 (2001-03-01), Sevic et al.
patent: 6566954 (2003-05-01), Miyazawa
patent: 6753734 (2004-06-01), Arell et al.
patent: 6956437 (2005-10-01), Lopez et al.

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