FET bias circuit

Details FET bias circuit FET bias circuit

2001-01-31

2002-11-26

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S083000

Reexamination Certificate

active

06486724

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for biasing a field effect transistor (FET).
2. Description of the Related Art
Circuits employing FETs, such as amplifiers, are used in radio frequency (RF) circuits for radio communications equipment.
FIG. 3
shows an example of an RF amplifier using an FET. The FET in the figure is, for example, a GaAs FET. This FET amplifies an input signal that is supplied to the gate from an input terminal IN via a capacitor C
1
and supplies an amplified signal from the drain to an output terminal OUT via a capacitor C
2
. The drain of the FET is connected to a positive power supply (+VDD) via a resistor Rd, the source is connected to ground, and the gate is connected to a negative power supply (−VSS) via a resistor Rg
2
.
Furthermore, a circuit for biasing the FET in
FIG. 3
is a regulated-current bias circuit that constantly maintains a drain bias current Idsdc at a fixed level and comprises a bipolar transistor Tr
1
, resistors Rb
1
, Rb
2
, Rg
1
, Rg
2
, and Rd, and a diode D
1
. One end of resistor Rb
1
is connected to the positive power supply (+VDD) and the other end is connected to the anode of diode D
1
. One end of resistor Rb
2
is connected to the cathode of diode D
1
and to the base of transistor Tr
1
, and the other end is connected to ground. Therefore, the series circuit formed from resistors Rb
1
and Rb
2
and diode D
1
is a dividing circuit for dividing the supply voltage VDD to generate voltage Vb and applying it to the base of transistor Tr
1
. The series circuit is also a temperature compensation circuit for compensating through diode D
1
a temperature dependency appearing in the base-emitter voltage of transistor Tr
1
and in turn the emitter current. In relation to this compensation operation, it should be noted that the collector of transistor Tr
1
is connected to the gate of the FET via resistor Rg
1
, and the emitter is connected to the drain of the FET. Since transistor Tr
1
is provided in this sort of configuration, the drain bias current Idsdc of the FET is held at a fixed value of Idsdc=(VDD−Vb−Vbe)/Rd mainly due to the action of the diode D
1
even if a change occurs in the emitter voltage of transistor Tr
1
due to a change in temperature. Furthermore, since the gate impedance of the FET, which is ideally infinite, is actually a finite value, a minute current flows to the gate of the FET. This gate current Igsdc is limited by resistors Rg
1
and Rg
2
, which are connected to the gate of the FET, so that the long-term reliability of the FET is maintained. Furthermore, since resistor Rg
1
is provided, the impedance when viewing the transistor Tr
1
from the FET is that much higher and the radio frequency amplification characteristics become more stable.
Regarding the regulation of the drain bias current Idsdc as a constant current, refer to Japanese Patent Laid-Open Publication No. Hei 7-321561. Regarding temperature compensation by the diode D
1
, refer to Japanese Patent Laid-Open Publication No. Hei 5-175747. Furthermore, the gate bias voltage, gate current, drain bias voltage, and drain bias current are respectively denoted in the figure by Vgsdc, Igsdc, Vdsdc, and Idsdc during no signal input and Vgsrf, Igsrf, Vdsrf, and Idsrf during signal amplification (when the output signal level is high). In the description hereinafter, Vgsdc, Igsdc, Vdsdc, and Idsdc are used for the symbols or variable names, unless whenever a distinction is required.
In the circuit shown in
FIG. 3
, the emitter current of transistor Tr
1
is supplied via resistor Rd. Thus, the power dissipation at resistor Rd is large compared to the circuit of
FIG. 4
to be described hereinafter. Furthermore, since the drain bias current Idsdc is regulated as a constant current, the circuit of
FIG. 3
cannot be used in a class AB or class B amplification mode in which the drain current varies according to the input signal level. Namely, the circuit of
FIG. 3
can only be used for class A amplification. Thus, it is difficult to achieve large power amplification at a high efficiency.
A regulated voltage bias circuit that does not have this type of problem is shown in FIG.
4
. In the circuit shown in this figure, the output voltage of the constant voltage source V
1
that is implemented from a resistance-type dividing circuit, a voltage regulator, an operational amplifier, and so forth, is applied to the gate of the FET via the resistor Rg. Since the circuit at the gate side of the FET is completely separate from the circuit at the drain side in the figure, the drain bias current Idsdc can be more freely set unlike the circuit of FIG.
3
. Therefore, the FET can be made to function in a class A, class AB, or class B configuration. Namely, by configuring the constant voltage source V
1
so that the output voltage can be adjusted and by adjusting the output voltage of the constant voltage source V
1
to an appropriate value, the gate bias voltage Vgsdc can be set to a target value, and in turn the drain bias current Idsdc can be set to an appropriate value. Thus, the circuit shown in
FIG. 4
can be used in various applications from small signal amplification in class A operation to large signal amplification in class AB or class B operation. Furthermore, the gate bias voltage Vgsdc is applied from the constant voltage source V
1
via resistor Rg. Thus, the gate bias current Idsdc is limited by resistor Rg so that the long-term reliability of the FET can be maintained. For the same reason, the impedance is high, when the constant voltage source V
1
is viewed from the FET, to further stabilize the RF amplification characteristics.
However, the above-mentioned conventional circuit has several problems.
First, a compensation circuit having a complex configuration becomes necessary when implementing the circuit shown in FIG.
4
. Here, the compensation circuit refers to a circuit for compensating for variations in the gate current Igs accompanying changes in the input signal level, temperature, and so forth. When the gate current Igsdc varies, the gate bias voltage Vgsdc and further the drain bias current Idsdc also varies as a result. More specifically, the amount of change &Dgr;Idsdc in the drain bias current Idsdc can be expressed in the following equation:
 &Dgr;
Idsdc
=(&Dgr;
Vgsdc
1
+&Dgr;
Vgsdc
2
)*(
gm+&Dgr;gm
)=(&Dgr;
Igsdc
1
+&Dgr;
Igsdc
2
)*(
gm+&Dgr;gm
)*
Rg
In this equation, &Dgr;Vgsdc
1
and &Dgr;Igsdc
1
are respectively the amount of change in the gate bias voltage Vgsdc and in the gate current Igsdc accompanying the change in input signal level, &Dgr;Vgsdc
2
and &Dgr;Igsdc
2
are respectively the amount of change in the gate bias voltage Vgsdc and in the gate current Igsdc accompanying the change in temperature, gm is the mutual conductance of the FET, and &Dgr;gm is the amount of change in gm accompanying the change in temperature.
Generally, &Dgr;Idsdc appearing in the equation is a quadratic function of temperature and &Dgr;gm is a linear function. Thus, with no temperature compensation, the temperature characteristic of the drain bias current Idsdc approximates the quadratic function characteristic, for example, as shown by the broken line in FIG.
5
. Obviously, so as to preferably compensate for this temperature characteristic, a temperature compensation circuit having a quadratic function characteristic is necessary. A temperature compensation circuit having such a characteristic generally has a complex configuration, and the use of such a temperature compensation circuit in configuring an RF amplifier results in an increase in circuit size and in the cost of the amplifier. However, if a temperature compensation circuit having a linear function characteristic is used thereby avoiding a complex circuit configuration, the temperature dependency is not well compensated and persists in the characteristic after temperature compensation, as shown by the solid line in FIG.
5
.
During no signal input,

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