FET bias circuit

Details FET bias circuit FET bias circuit

2011-05-24

2011-05-24

Nguyen, Hieu P (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including particular biasing arrangement

C330S277000

Reexamination Certificate

active

07948321

ABSTRACT:
A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

REFERENCES:
patent: 6255910 (2001-07-01), Forstner
patent: 7190935 (2007-03-01), Hecht
patent: 7202743 (2007-04-01), Enomoto
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Written Opinion of the International Searching Authority for International Application No. PCT/JP2006/313404 with English translation.
International Search Report for International Application No. PCT/JP2006/313404 mailed Oct. 10, 2006 with English translation.
Japanese Office Action for Japanese Patent application No. 2005-196492 mailed Dec. 4, 2007 with English translation.
Notice of Grounds for Rejection for Patent Application Serial No. 2005-196492 mailed Aug. 14, 2007 with English translation.

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